From patchwork Tue Nov 5 12:55:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 3141921 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0ED3D9F407 for ; Tue, 5 Nov 2013 14:25:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CE7EC2058E for ; Tue, 5 Nov 2013 14:25:28 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 101B220597 for ; Tue, 5 Nov 2013 14:25:24 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VdgDa-00007u-6Y; Tue, 05 Nov 2013 12:58:51 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VdgCl-0000Ah-67; Tue, 05 Nov 2013 12:57:59 +0000 Received: from top.free-electrons.com ([176.31.233.9] helo=mail.free-electrons.com) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VdgB8-0008KU-1a; Tue, 05 Nov 2013 12:56:18 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 4341A825; Tue, 5 Nov 2013 13:56:27 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (unknown [190.2.98.212]) by mail.free-electrons.com (Postfix) with ESMTPA id 6B75D7E4; Tue, 5 Nov 2013 13:56:23 +0100 (CET) From: Ezequiel Garcia To: , Subject: [PATCH v3 10/28] mtd: nand: pxa3xx: Replace host->page_size by mtd->writesize Date: Tue, 5 Nov 2013 09:55:17 -0300 Message-Id: <1383656135-8627-11-git-send-email-ezequiel.garcia@free-electrons.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1383656135-8627-1-git-send-email-ezequiel.garcia@free-electrons.com> References: <1383656135-8627-1-git-send-email-ezequiel.garcia@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131105_075618_198406_E2E1791F X-CRM114-Status: GOOD ( 10.88 ) X-Spam-Score: -1.2 (-) Cc: Lior Amsalem , Thomas Petazzoni , Jason Cooper , Tawfik Bayouk , Daniel Mack , Huang Shijie , Ezequiel Garcia , Gregory Clement , Brian Norris , Willy Tarreau X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP There's no need to privately store the device page size as it's available in mtd structure field mtd->writesize. Also, this removes the hardcoded page size value, leaving the auto-detected value only. Signed-off-by: Ezequiel Garcia --- drivers/mtd/nand/pxa3xx_nand.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 1fc9e6d..c558cadb 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -149,7 +149,6 @@ struct pxa3xx_nand_host { void *info_data; /* page size of attached chip */ - unsigned int page_size; int use_ecc; int cs; @@ -612,12 +611,12 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, info->buf_start += mtd->writesize; /* Second command setting for large pages */ - if (host->page_size >= PAGE_CHUNK_SIZE) + if (mtd->writesize >= PAGE_CHUNK_SIZE) info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); case NAND_CMD_SEQIN: /* small page addr setting */ - if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) { + if (unlikely(mtd->writesize < PAGE_CHUNK_SIZE)) { info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) | (column & 0xFF); @@ -891,7 +890,6 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, } /* calculate flash information */ - host->page_size = f->page_size; host->read_id_bytes = (f->page_size == 2048) ? 4 : 2; /* calculate addressing information */ @@ -930,11 +928,9 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) if (ndcr & NDCR_PAGE_SZ) { /* Controller's FIFO size */ info->fifo_size = 2048; - host->page_size = 2048; host->read_id_bytes = 4; } else { info->fifo_size = 512; - host->page_size = 512; host->read_id_bytes = 2; } @@ -1102,7 +1098,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd) def = pxa3xx_flash_ids; KEEP_CONFIG: chip->ecc.mode = NAND_ECC_HW; - chip->ecc.size = host->page_size; + chip->ecc.size = info->fifo_size; chip->ecc.strength = 1; if (info->reg_ndcr & NDCR_DWIDTH_M)