From patchwork Fri Nov 8 09:00:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shiyan X-Patchwork-Id: 3156881 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BAC32BEEB2 for ; Fri, 8 Nov 2013 09:01:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9AD4E20495 for ; Fri, 8 Nov 2013 09:01:19 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 52C6E20494 for ; Fri, 8 Nov 2013 09:01:14 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vehw7-0006eU-VC; Fri, 08 Nov 2013 09:01:04 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vehw5-0006H8-Lv; Fri, 08 Nov 2013 09:01:01 +0000 Received: from smtp53.i.mail.ru ([94.100.177.113]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vehw2-0006Gq-32 for linux-arm-kernel@lists.infradead.org; Fri, 08 Nov 2013 09:00:59 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=Message-Id:Date:Subject:Cc:To:From; bh=oByJEOz12gm/VRLWcjw2TFOG4MqcVrhwMECMnJiA1lM=; b=cj6NfRS6WvsCdy41jbVpGeMagxx1ftRbwZUsJHbapJovd+ZexC6BU/ylW3QP794/5uhjH/6eC1qM8RyfNMclSybZFcZxmG8ieRA6qky5jMj/nu8Oo13MQ2L6kMb2n6dOu+IaqpMUul/8hDpjWhN+tLmKmTDhJ9jMA58xXHbvNbE=; Received: from [217.119.30.118] (port=62847 helo=shc.milas.spb.ru) by smtp53.i.mail.ru with esmtpa (envelope-from ) id 1Vehve-00036M-56; Fri, 08 Nov 2013 13:00:34 +0400 From: Alexander Shiyan To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: i.MX5x: Add SAHARA clock for i.MX5x CPUs Date: Fri, 8 Nov 2013 13:00:22 +0400 Message-Id: <1383901222-12013-1-git-send-email-shc_work@mail.ru> X-Mailer: git-send-email 1.8.1.5 X-Mras: Ok X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131108_040058_597780_781E69EE X-CRM114-Status: UNSURE ( 9.12 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.2 (-) Cc: Shawn Guo , Russell King , Alexander Shiyan , Sascha Hauer X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, FREEMAIL_FROM,RCVD_IN_DNSWL_MED,RCVD_IN_SORBS_WEB,RP_MATCHES_RCVD, T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Patch adds missing Security Accelerator (SAHARA) clock for i.MX5x CPUs. Signed-off-by: Alexander Shiyan --- Documentation/devicetree/bindings/clock/imx5-clock.txt | 1 + arch/arm/mach-imx/clk-imx51-imx53.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt index 4c029a8..a8bbe77 100644 --- a/Documentation/devicetree/bindings/clock/imx5-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt @@ -198,6 +198,7 @@ clocks and IDs. spdif1_gate 184 spdif_ipg_gate 185 ocram 186 + sahara_ipg_gate 187 Examples (for mx53): diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index 219c65e..931f7f9 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -123,7 +123,7 @@ enum imx5_clks { srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel, spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf, spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate, - ocram, clk_max + ocram, sahara_ipg_gate, clk_max }; static struct clk *clk[clk_max]; @@ -286,6 +286,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT); clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); + clk[sahara_ipg_gate] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); for (i = 0; i < ARRAY_SIZE(clk); i++) if (IS_ERR(clk[i]))