From patchwork Fri Nov 8 10:11:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 3157261 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0FCE2BEEB2 for ; Fri, 8 Nov 2013 10:14:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C8EE3202F8 for ; Fri, 8 Nov 2013 10:14:07 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EFFAE202BE for ; Fri, 8 Nov 2013 10:14:02 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vej3n-0004WQ-Lt; Fri, 08 Nov 2013 10:13:04 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vej3b-0007lB-Jx; Fri, 08 Nov 2013 10:12:51 +0000 Received: from mail-pb0-x234.google.com ([2607:f8b0:400e:c01::234]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vej3Y-0007ir-A5 for linux-arm-kernel@lists.infradead.org; Fri, 08 Nov 2013 10:12:49 +0000 Received: by mail-pb0-f52.google.com with SMTP id rr4so1933223pbb.25 for ; Fri, 08 Nov 2013 02:12:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0yOknI/1z/gTpLcY/YIcyLGjwUnNcZSj6H92GkosWtM=; b=wa9gk8zB2+/aiJS1P1UJxx5QLkoVfxT5sU/psbl6BxDPBfUxjMZL+auRS3otQsa0iM 2VY5jlfvX2fsj6ovA6sout8Mrm69yfZlNhQxxE/cJIfCH7mrnwEKLYlrlSdC/uQtZs+z oMAOTFvmjz6P4L2pn+1TxGXa3ZQ+zFmP3tfl8KiJDwkcyZoAPXf8ANJ78Bpf34REl7aK z8eUdOcoK1GpxB16yvma+jg+DgOidmN+3w/ZcspTdcRU+pPl5yG3RyQlKNxoj3CNnmuo 70XVIjKvT9F4fEYK7t+DQWqxTsBR55oH9QEmHUlg4Kd0/qBqCkki3oy4U4P6Jp5DLtLH oCTQ== X-Received: by 10.68.218.165 with SMTP id ph5mr13991224pbc.11.1383905543922; Fri, 08 Nov 2013 02:12:23 -0800 (PST) Received: from localhost.localdomain ([182.156.67.248]) by mx.google.com with ESMTPSA id fa4sm13061280pab.17.2013.11.08.02.12.15 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 08 Nov 2013 02:12:22 -0800 (PST) From: Prabhakar Lad To: Sekhar Nori , Linus Walleij , Grygorii Strashko Subject: [PATCH v5 2/7] gpio: davinci: use readl/writel instead of __raw_* Date: Fri, 8 Nov 2013 15:41:45 +0530 Message-Id: <1383905510-31760-3-git-send-email-prabhakar.csengg@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1383905510-31760-1-git-send-email-prabhakar.csengg@gmail.com> References: <1383905510-31760-1-git-send-email-prabhakar.csengg@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131108_051248_545118_EB62FEFB X-CRM114-Status: GOOD ( 16.44 ) X-Spam-Score: -2.0 (--) Cc: Mark Rutland , devicetree@vger.kernel.org, DLOS , Pawel Moll , linux-doc@vger.kernel.org, Stephen Warren , LKML , Rob Herring , linux-gpio@vger.kernel.org, Prabhakar Lad , Rob Landley , Grant Likely , Ian Campbell , LAK X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Lad, Prabhakar" This patch replaces the __raw_readl/writel with readl and writel, Although the code runs on ARMv5 based SOCs, changing this will help copying the code for other uses. Signed-off-by: Lad, Prabhakar Acked-by: Linus Walleij --- drivers/gpio/gpio-davinci.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index 7230c43..ca3d7fd 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -82,14 +82,14 @@ static inline int __davinci_direction(struct gpio_chip *chip, u32 mask = 1 << offset; spin_lock_irqsave(&d->lock, flags); - temp = __raw_readl(&g->dir); + temp = readl(&g->dir); if (out) { temp &= ~mask; - __raw_writel(mask, value ? &g->set_data : &g->clr_data); + writel(mask, value ? &g->set_data : &g->clr_data); } else { temp |= mask; } - __raw_writel(temp, &g->dir); + writel(temp, &g->dir); spin_unlock_irqrestore(&d->lock, flags); return 0; @@ -118,7 +118,7 @@ static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) struct davinci_gpio_controller *d = chip2controller(chip); struct davinci_gpio_regs __iomem *g = d->regs; - return (1 << offset) & __raw_readl(&g->in_data); + return (1 << offset) & readl(&g->in_data); } /* @@ -130,7 +130,7 @@ davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) struct davinci_gpio_controller *d = chip2controller(chip); struct davinci_gpio_regs __iomem *g = d->regs; - __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); + writel((1 << offset), value ? &g->set_data : &g->clr_data); } static int davinci_gpio_probe(struct platform_device *pdev) @@ -227,8 +227,8 @@ static void gpio_irq_disable(struct irq_data *d) struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); u32 mask = (u32) irq_data_get_irq_handler_data(d); - __raw_writel(mask, &g->clr_falling); - __raw_writel(mask, &g->clr_rising); + writel(mask, &g->clr_falling); + writel(mask, &g->clr_rising); } static void gpio_irq_enable(struct irq_data *d) @@ -242,9 +242,9 @@ static void gpio_irq_enable(struct irq_data *d) status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; if (status & IRQ_TYPE_EDGE_FALLING) - __raw_writel(mask, &g->set_falling); + writel(mask, &g->set_falling); if (status & IRQ_TYPE_EDGE_RISING) - __raw_writel(mask, &g->set_rising); + writel(mask, &g->set_rising); } static int gpio_irq_type(struct irq_data *d, unsigned trigger) @@ -286,10 +286,10 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) int res; /* ack any irqs */ - status = __raw_readl(&g->intstat) & mask; + status = readl(&g->intstat) & mask; if (!status) break; - __raw_writel(status, &g->intstat); + writel(status, &g->intstat); /* now demux them to the right lowlevel handler */ n = d->irq_base; @@ -346,9 +346,9 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) return -EINVAL; - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) + writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) ? &g->set_falling : &g->clr_falling); - __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) + writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) ? &g->set_rising : &g->clr_rising); return 0; @@ -430,8 +430,8 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) /* default trigger: both edges */ g = gpio2regs(0); - __raw_writel(~0, &g->set_falling); - __raw_writel(~0, &g->set_rising); + writel(~0, &g->set_falling); + writel(~0, &g->set_rising); /* set the direct IRQs up to use that irqchip */ for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) { @@ -454,8 +454,8 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) /* disabled by default, enabled only as needed */ g = gpio2regs(gpio); - __raw_writel(~0, &g->clr_falling); - __raw_writel(~0, &g->clr_rising); + writel(~0, &g->clr_falling); + writel(~0, &g->clr_rising); /* set up all irqs in this bank */ irq_set_chained_handler(bank_irq, gpio_irq_handler); @@ -483,7 +483,7 @@ done: * BINTEN -- per-bank interrupt enable. genirq would also let these * bits be set/cleared dynamically. */ - __raw_writel(binten, gpio_base + BINTEN); + writel(binten, gpio_base + BINTEN); printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));