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[97.117.182.57]) by mx.google.com with ESMTPSA id rx4sm48238628pab.13.2013.11.20.21.35.38 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 20 Nov 2013 21:35:39 -0800 (PST) Received: from tkisky by officeserver-2 with local (Exim 4.80) (envelope-from ) id 1VjMvE-0006AW-H6; Wed, 20 Nov 2013 22:35:24 -0700 From: Troy Kisky To: shawn.guo@linaro.org Subject: [PATCH V2 1/1] ARM: dts: imx: imx6sl/qdl-pingrp: reorganize USDHCx pad groups Date: Wed, 20 Nov 2013 22:35:22 -0700 Message-Id: <1385012122-23681-1-git-send-email-troy.kisky@boundarydevices.com> X-Mailer: git-send-email 1.8.1.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131121_003607_760864_2224B379 X-CRM114-Status: UNSURE ( 9.51 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) Cc: festevam@gmail.com, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org, Troy Kisky X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use helper macros to avoid repetition. Signed-off-by: Troy Kisky v2: added pad_data3 as a macro argument as suggested by Russell King --- arch/arm/boot/dts/imx6q-arm2.dts | 4 +- arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 2 +- arch/arm/boot/dts/imx6q-gw5400-a.dts | 2 +- arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi | 4 +- arch/arm/boot/dts/imx6q-sabrelite.dts | 4 +- arch/arm/boot/dts/imx6q-sbc6x.dts | 2 +- arch/arm/boot/dts/imx6q-udoo.dts | 2 +- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 +- arch/arm/boot/dts/imx6qdl-pingrp.h | 192 +++++++++++++---------------- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 6 +- arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 4 +- arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 6 +- arch/arm/boot/dts/imx6sl-evk.dts | 18 +-- arch/arm/boot/dts/imx6sl-pingrp.h | 173 +++++++++++++------------- 16 files changed, 209 insertions(+), 216 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index ff922cc..9c00b73 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -95,7 +95,7 @@ }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc3_cdwp: usdhc3cdwp { @@ -106,7 +106,7 @@ }; pinctrl_usdhc4: usdhc4grp { - fsl,pins = ; + fsl,pins = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index 5d6bab3..84f5143 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -139,7 +139,7 @@ }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 63c641d..5f76342 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -427,7 +427,7 @@ }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi index 0519903..05b4796 100644 --- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi @@ -154,11 +154,11 @@ }; pinctrl_usdhc2: usdhc2grp { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc3_cdwp: usdhc3cdwp { diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index ec9e4c1..b5f0edd 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -156,11 +156,11 @@ }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc4: usdhc4grp { - fsl,pins = ; + fsl,pins = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts index 230977f..852675a 100644 --- a/arch/arm/boot/dts/imx6q-sbc6x.dts +++ b/arch/arm/boot/dts/imx6q-sbc6x.dts @@ -40,7 +40,7 @@ }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts index 1c7f7a1..47a5eda 100644 --- a/arch/arm/boot/dts/imx6q-udoo.dts +++ b/arch/arm/boot/dts/imx6q-udoo.dts @@ -39,7 +39,7 @@ }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index ffc1e66..a6c77b5 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -363,7 +363,7 @@ }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 79c2589..35028a5 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -400,7 +400,7 @@ }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index cb112d3..34b26b9 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -422,7 +422,7 @@ }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-pingrp.h b/arch/arm/boot/dts/imx6qdl-pingrp.h index d111e59..6cb7dba 100644 --- a/arch/arm/boot/dts/imx6qdl-pingrp.h +++ b/arch/arm/boot/dts/imx6qdl-pingrp.h @@ -387,109 +387,95 @@ #define MX6QDL_USBH3_PINGRP2 \ MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 -#define MX6QDL_USDHC1_PINGRP1 \ - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 \ - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 \ - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 \ - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 \ - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 \ - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 \ - MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059 \ - MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059 \ - MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059 \ - MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059 - -#define MX6QDL_USDHC1_PINGRP2 \ - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 \ - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 \ - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 \ - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 \ - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 \ - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - -#define MX6QDL_USDHC2_PINGRP1 \ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 \ - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 \ - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 \ - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 \ - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 \ - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 \ - MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 \ - MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 \ - MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 \ - MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 - -#define MX6QDL_USDHC2_PINGRP2 \ - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 \ - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 \ - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 \ - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 \ - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 \ - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - -#define MX6QDL_USDHC3_PINGRP1 \ - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 \ - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 \ - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 \ - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 \ - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 \ - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 \ - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 \ - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 \ - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 \ - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 - -#define MX6QDL_USDHC3_PINGRP1_100MHZ \ - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 \ - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 \ - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 \ - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 \ - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 \ - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 \ - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 \ - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 \ - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 \ - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - -#define MX6QDL_USDHC3_PINGRP1_200MHZ \ - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 \ - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 \ - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 \ - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 \ - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 \ - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 \ - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 \ - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 \ - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 \ - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - -#define MX6QDL_USDHC3_PINGRP2 \ - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 \ - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 \ - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 \ - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 \ - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 \ - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - -#define MX6QDL_USDHC4_PINGRP1 \ - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 \ - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 \ - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 \ - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 \ - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 \ - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 \ - MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 \ - MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 \ - MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 \ - MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 - -#define MX6QDL_USDHC4_PINGRP2 \ - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 \ - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 \ - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 \ - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 \ - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 \ - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 +#define MX6QDL_USDHC1_D4(pad, pad_data3, pad_clk) \ + MX6QDL_PAD_SD1_CMD__SD1_CMD pad \ + MX6QDL_PAD_SD1_CLK__SD1_CLK pad_clk \ + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 pad \ + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 pad \ + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 pad \ + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 pad_data3 + +#define MX6QDL_USDHC1_D8(pad, pad_data3, pad_clk) \ + MX6QDL_USDHC1_D4(pad, pad_data3, pad_clk) \ + MX6QDL_PAD_NANDF_D0__SD1_DATA4 pad \ + MX6QDL_PAD_NANDF_D1__SD1_DATA5 pad \ + MX6QDL_PAD_NANDF_D2__SD1_DATA6 pad \ + MX6QDL_PAD_NANDF_D3__SD1_DATA7 pad + + +#define MX6QDL_USDHC2_D4(pad, pad_data3, pad_clk) \ + MX6QDL_PAD_SD2_CMD__SD2_CMD pad \ + MX6QDL_PAD_SD2_CLK__SD2_CLK pad_clk \ + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 pad \ + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 pad \ + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 pad \ + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 pad_data3 + +#define MX6QDL_USDHC2_D8(pad, pad_data3, pad_clk) \ + MX6QDL_USDHC2_D4(pad, pad_data3, pad_clk) \ + MX6QDL_PAD_NANDF_D4__SD2_DATA4 pad \ + MX6QDL_PAD_NANDF_D5__SD2_DATA5 pad \ + MX6QDL_PAD_NANDF_D6__SD2_DATA6 pad \ + MX6QDL_PAD_NANDF_D7__SD2_DATA7 pad + + +#define MX6QDL_USDHC3_D4(pad, pad_data3, pad_clk) \ + MX6QDL_PAD_SD3_CMD__SD3_CMD pad \ + MX6QDL_PAD_SD3_CLK__SD3_CLK pad_clk \ + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 pad \ + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 pad \ + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 pad \ + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 pad_data3 + +#define MX6QDL_USDHC3_D8(pad, pad_data3, pad_clk) \ + MX6QDL_USDHC3_D4(pad, pad_data3, pad_clk) \ + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 pad \ + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 pad \ + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 pad \ + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 pad + +#define MX6QDL_USDHC4_D4(pad, pad_data3, pad_clk) \ + MX6QDL_PAD_SD4_CMD__SD4_CMD pad \ + MX6QDL_PAD_SD4_CLK__SD4_CLK pad_clk \ + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 pad \ + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 pad \ + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 pad \ + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 pad_data3 + +#define MX6QDL_USDHC4_D8(pad, pad_data3, pad_clk) \ + MX6QDL_USDHC4_D4(pad, pad_data3, pad_clk) \ + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 pad \ + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 pad \ + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 pad \ + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 pad + +#define MX6QDL_USDHC1_PINGRP_D4 MX6QDL_USDHC1_D4(0x17059,0x17059,0x10059) +#define MX6QDL_USDHC1_PINGRP_D4_100MHZ MX6QDL_USDHC1_D4(0x170b9,0x170b9,0x100b9) +#define MX6QDL_USDHC1_PINGRP_D4_200MHZ MX6QDL_USDHC1_D4(0x170f9,0x170f9,0x100f9) +#define MX6QDL_USDHC1_PINGRP_D8 MX6QDL_USDHC1_D8(0x17059,0x17059,0x10059) +#define MX6QDL_USDHC1_PINGRP_D8_100MHZ MX6QDL_USDHC1_D8(0x170b9,0x170b9,0x100b9) +#define MX6QDL_USDHC1_PINGRP_D8_200MHZ MX6QDL_USDHC1_D8(0x170f9,0x170f9,0x100f9) + +#define MX6QDL_USDHC2_PINGRP_D4 MX6QDL_USDHC2_D4(0x17059,0x17059,0x10059) +#define MX6QDL_USDHC2_PINGRP_D4_100MHZ MX6QDL_USDHC2_D4(0x170b9,0x170b9,0x100b9) +#define MX6QDL_USDHC2_PINGRP_D4_200MHZ MX6QDL_USDHC2_D4(0x170f9,0x170f9,0x100f9) +#define MX6QDL_USDHC2_PINGRP_D8 MX6QDL_USDHC2_D8(0x17059,0x17059,0x10059) +#define MX6QDL_USDHC2_PINGRP_D8_100MHZ MX6QDL_USDHC2_D8(0x170b9,0x170b9,0x100b9) +#define MX6QDL_USDHC2_PINGRP_D8_200MHZ MX6QDL_USDHC2_D8(0x170f9,0x170f9,0x100f9) + +#define MX6QDL_USDHC3_PINGRP_D4 MX6QDL_USDHC3_D4(0x17059,0x17059,0x10059) +#define MX6QDL_USDHC3_PINGRP_D4_100MHZ MX6QDL_USDHC3_D4(0x170b9,0x170b9,0x100b9) +#define MX6QDL_USDHC3_PINGRP_D4_200MHZ MX6QDL_USDHC3_D4(0x170f9,0x170f9,0x100f9) +#define MX6QDL_USDHC3_PINGRP_D8 MX6QDL_USDHC3_D8(0x17059,0x17059,0x10059) +#define MX6QDL_USDHC3_PINGRP_D8_100MHZ MX6QDL_USDHC3_D8(0x170b9,0x170b9,0x100b9) +#define MX6QDL_USDHC3_PINGRP_D8_200MHZ MX6QDL_USDHC3_D8(0x170f9,0x170f9,0x100f9) + +#define MX6QDL_USDHC4_PINGRP_D4 MX6QDL_USDHC4_D4(0x17059,0x17059,0x10059) +#define MX6QDL_USDHC4_PINGRP_D4_100MHZ MX6QDL_USDHC4_D4(0x170b9,0x170b9,0x100b9) +#define MX6QDL_USDHC4_PINGRP_D4_200MHZ MX6QDL_USDHC4_D4(0x170f9,0x170f9,0x100f9) +#define MX6QDL_USDHC4_PINGRP_D8 MX6QDL_USDHC4_D8(0x17059,0x17059,0x10059) +#define MX6QDL_USDHC4_PINGRP_D8_100MHZ MX6QDL_USDHC4_D8(0x170b9,0x170b9,0x100b9) +#define MX6QDL_USDHC4_PINGRP_D8_200MHZ MX6QDL_USDHC4_D8(0x170f9,0x170f9,0x100f9) #define MX6QDL_WEIM_CS0_PINGRP1 \ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 719c3a7..a526796 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -81,15 +81,15 @@ }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = ; + fsl,pins = ; }; pinctrl_weim_cs0: weimcs0grp { diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 4239ef9..570767f 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -223,11 +223,11 @@ }; pinctrl_usdhc2: usdhc2grp { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 10ed94a..88894b1 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -125,15 +125,15 @@ }; pinctrl_usdhc1: usdhc1grp { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc2: usdhc2grp { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index e565989..f5e4513 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -102,39 +102,39 @@ }; pinctrl_usdhc1: usdhc1grp { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc2: usdhc2grp { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc3: usdhc3grp { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = ; + fsl,pins = ; }; pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = ; + fsl,pins = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6sl-pingrp.h b/arch/arm/boot/dts/imx6sl-pingrp.h index 984077b..72ad594 100644 --- a/arch/arm/boot/dts/imx6sl-pingrp.h +++ b/arch/arm/boot/dts/imx6sl-pingrp.h @@ -57,88 +57,95 @@ #define MX6SL_USBOTG2_PINGRP4 \ MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059 -#define MX6SL_USDHC1_PINGRP1 \ - MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 \ - MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 \ - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 \ - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 \ - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 \ - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 \ - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 \ - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 \ - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 \ - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 - -#define MX6SL_USDHC1_PINGRP1_100MHZ \ - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 \ - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9 \ - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 \ - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 \ - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 \ - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 \ - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 \ - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 \ - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 \ - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 - -#define MX6SL_USDHC1_PINGRP1_200MHZ \ - MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 \ - MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9 \ - MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 \ - MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 \ - MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 \ - MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 \ - MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9 \ - MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9 \ - MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9 \ - MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9 - -#define MX6SL_USDHC2_PINGRP1 \ - MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 \ - MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059 \ - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 \ - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 \ - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 \ - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 - -#define MX6SL_USDHC2_PINGRP1_100MHZ \ - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 \ - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9 \ - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 \ - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 \ - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 \ - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 - -#define MX6SL_USDHC2_PINGRP1_200MHZ \ - MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 \ - MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9 \ - MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 \ - MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 \ - MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 \ - MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 - -#define MX6SL_USDHC3_PINGRP1 \ - MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059 \ - MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059 \ - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059 \ - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059 \ - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059 \ - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059 - -#define MX6SL_USDHC3_PINGRP1_100MHZ \ - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 \ - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9 \ - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 \ - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 \ - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 \ - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - -#define MX6SL_USDHC3_PINGRP1_200MHZ \ - MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 \ - MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9 \ - MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 \ - MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 \ - MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 \ - MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + +#define MX6SL_USDHC1_D4(pad, pad_data3, pad_clk) \ + MX6SL_PAD_SD1_CMD__SD1_CMD pad \ + MX6SL_PAD_SD1_CLK__SD1_CLK pad_clk \ + MX6SL_PAD_SD1_DAT0__SD1_DATA0 pad \ + MX6SL_PAD_SD1_DAT1__SD1_DATA1 pad \ + MX6SL_PAD_SD1_DAT2__SD1_DATA2 pad \ + MX6SL_PAD_SD1_DAT3__SD1_DATA3 pad_data3 + +#define MX6SL_USDHC1_D8(pad, pad_data3, pad_clk) \ + MX6SL_USDHC1_D4(pad, pad_data3, pad_clk) \ + MX6SL_PAD_SD1_DAT4__SD1_DATA4 pad \ + MX6SL_PAD_SD1_DAT5__SD1_DATA5 pad \ + MX6SL_PAD_SD1_DAT6__SD1_DATA6 pad \ + MX6SL_PAD_SD1_DAT7__SD1_DATA7 pad + + +#define MX6SL_USDHC2_D4(pad, pad_data3, pad_clk) \ + MX6SL_PAD_SD2_CMD__SD2_CMD pad \ + MX6SL_PAD_SD2_CLK__SD2_CLK pad_clk \ + MX6SL_PAD_SD2_DAT0__SD2_DATA0 pad \ + MX6SL_PAD_SD2_DAT1__SD2_DATA1 pad \ + MX6SL_PAD_SD2_DAT2__SD2_DATA2 pad \ + MX6SL_PAD_SD2_DAT3__SD2_DATA3 pad_data3 + +#define MX6SL_USDHC2_D8(pad, pad_data3, pad_clk) \ + MX6SL_USDHC2_D4(pad, pad_data3, pad_clk) \ + MX6SL_PAD_SD2_DAT4__SD2_DATA4 pad \ + MX6SL_PAD_SD2_DAT5__SD2_DATA5 pad \ + MX6SL_PAD_SD2_DAT6__SD2_DATA6 pad \ + MX6SL_PAD_SD2_DAT7__SD2_DATA7 pad + + +#define MX6SL_USDHC3_D4(pad, pad_data3, pad_clk) \ + MX6SL_PAD_SD3_CMD__SD3_CMD pad \ + MX6SL_PAD_SD3_CLK__SD3_CLK pad_clk \ + MX6SL_PAD_SD3_DAT0__SD3_DATA0 pad \ + MX6SL_PAD_SD3_DAT1__SD3_DATA1 pad \ + MX6SL_PAD_SD3_DAT2__SD3_DATA2 pad \ + MX6SL_PAD_SD3_DAT3__SD3_DATA3 pad_data3 + +#define MX6SL_USDHC3_D8(pad, pad_data3, pad_clk) \ + MX6SL_USDHC3_D4(pad, pad_data3, pad_clk) \ + MX6SL_PAD_SD2_DAT4__SD3_DATA4 pad \ + MX6SL_PAD_SD2_DAT5__SD3_DATA5 pad \ + MX6SL_PAD_SD2_DAT6__SD3_DATA6 pad \ + MX6SL_PAD_SD2_DAT7__SD3_DATA7 pad + +#define MX6SL_USDHC4_D4(pad, pad_data3, pad_clk) \ + MX6SL_PAD_EPDC_BDR1__SD4_CMD pad \ + MX6SL_PAD_EPDC_BDR0__SD4_CLK pad_clk \ + MX6SL_PAD_EPDC_PWRCOM__SD4_DATA0 pad \ + MX6SL_PAD_EPDC_PWRINT__SD4_DATA1 pad \ + MX6SL_PAD_EPDC_PWRSTAT__SD4_DATA2 pad \ + MX6SL_PAD_EPDC_PWRWAKEUP__SD4_DATA3 pad_data3 + +#define MX6SL_USDHC4_D8(pad, pad_data3, pad_clk) \ + MX6SL_USDHC4_D4(pad, pad_data3, pad_clk) \ + MX6SL_PAD_KEY_COL7__SD4_DATA4 pad \ + MX6SL_PAD_KEY_ROW7__SD4_DATA5 pad \ + MX6SL_PAD_KEY_COL3__SD4_DATA6 pad \ + MX6SL_PAD_KEY_ROW3__SD4_DATA7 pad + +#define MX6SL_USDHC1_PINGRP_D4 MX6SL_USDHC1_D4(0x17059, 0x17059, 0x10059) +#define MX6SL_USDHC1_PINGRP_D4_100MHZ MX6SL_USDHC1_D4(0x170b9, 0x170b9, 0x100b9) +#define MX6SL_USDHC1_PINGRP_D4_200MHZ MX6SL_USDHC1_D4(0x170f9, 0x170f9, 0x100f9) +#define MX6SL_USDHC1_PINGRP_D8 MX6SL_USDHC1_D8(0x17059, 0x17059, 0x10059) +#define MX6SL_USDHC1_PINGRP_D8_100MHZ MX6SL_USDHC1_D8(0x170b9, 0x170b9, 0x100b9) +#define MX6SL_USDHC1_PINGRP_D8_200MHZ MX6SL_USDHC1_D8(0x170f9, 0x170f9, 0x100f9) + +#define MX6SL_USDHC2_PINGRP_D4 MX6SL_USDHC2_D4(0x17059, 0x17059, 0x10059) +#define MX6SL_USDHC2_PINGRP_D4_100MHZ MX6SL_USDHC2_D4(0x170b9, 0x170b9, 0x100b9) +#define MX6SL_USDHC2_PINGRP_D4_200MHZ MX6SL_USDHC2_D4(0x170f9, 0x170f9, 0x100f9) +#define MX6SL_USDHC2_PINGRP_D8 MX6SL_USDHC2_D8(0x17059, 0x17059, 0x10059) +#define MX6SL_USDHC2_PINGRP_D8_100MHZ MX6SL_USDHC2_D8(0x170b9, 0x170b9, 0x100b9) +#define MX6SL_USDHC2_PINGRP_D8_200MHZ MX6SL_USDHC2_D8(0x170f9, 0x170f9, 0x100f9) + +#define MX6SL_USDHC3_PINGRP_D4 MX6SL_USDHC3_D4(0x17059, 0x17059, 0x10059) +#define MX6SL_USDHC3_PINGRP_D4_100MHZ MX6SL_USDHC3_D4(0x170b9, 0x170b9, 0x100b9) +#define MX6SL_USDHC3_PINGRP_D4_200MHZ MX6SL_USDHC3_D4(0x170f9, 0x170f9, 0x100f9) +#define MX6SL_USDHC3_PINGRP_D8 MX6SL_USDHC3_D8(0x17059, 0x17059, 0x10059) +#define MX6SL_USDHC3_PINGRP_D8_100MHZ MX6SL_USDHC3_D8(0x170b9, 0x170b9, 0x100b9) +#define MX6SL_USDHC3_PINGRP_D8_200MHZ MX6SL_USDHC3_D8(0x170f9, 0x170f9, 0x100f9) + +#define MX6SL_USDHC4_PINGRP_D4 MX6SL_USDHC4_D4(0x17059, 0x17059, 0x10059) +#define MX6SL_USDHC4_PINGRP_D4_100MHZ MX6SL_USDHC4_D4(0x170b9, 0x170b9, 0x100b9) +#define MX6SL_USDHC4_PINGRP_D4_200MHZ MX6SL_USDHC4_D4(0x170f9, 0x170f9, 0x100f9) +#define MX6SL_USDHC4_PINGRP_D8 MX6SL_USDHC4_D8(0x17059, 0x17059, 0x10059) +#define MX6SL_USDHC4_PINGRP_D8_100MHZ MX6SL_USDHC4_D8(0x170b9, 0x170b9, 0x100b9) +#define MX6SL_USDHC4_PINGRP_D8_200MHZ MX6SL_USDHC4_D8(0x170f9, 0x170f9, 0x100f9) #endif /* __DTS_IMX6SL_PINGRP_H */