From patchwork Thu Nov 21 13:40:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 3218571 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 31F57C045B for ; Thu, 21 Nov 2013 14:07:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B817E2074B for ; Thu, 21 Nov 2013 14:07:05 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CBE3F20716 for ; Thu, 21 Nov 2013 14:07:00 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjUZ7-00051r-VX; Thu, 21 Nov 2013 13:45:07 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjUYE-0003GT-MN; Thu, 21 Nov 2013 13:44:10 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VjUWR-00032z-35 for linux-arm-kernel@lists.infradead.org; Thu, 21 Nov 2013 13:42:27 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 21 Nov 2013 05:41:43 -0800 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 21 Nov 2013 05:39:53 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 21 Nov 2013 05:39:53 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.327.1; Thu, 21 Nov 2013 05:41:58 -0800 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Thu, 21 Nov 2013 05:41:58 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id rALDf0sE014302; Thu, 21 Nov 2013 05:41:54 -0800 (PST) From: Hiroshi Doyu To: , , , , , , Subject: [PATCHv6 13/13] [FOR TEST] ARM: dt: tegra30: add "iommus" binding Date: Thu, 21 Nov 2013 15:40:49 +0200 Message-ID: <1385041249-7705-14-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1385041249-7705-1-git-send-email-hdoyu@nvidia.com> References: <1385041249-7705-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131121_084219_365630_60B0A278 X-CRM114-Status: GOOD ( 10.26 ) X-Spam-Score: -2.4 (--) Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, galak@codeaurora.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Hiroshi Doyu X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP "iommus" binding implies that a device can be attached to IOMMU devices. An iommu device needs to set #iommus-cells in it. "iommus" can have multiple iommu device phandles as below if needed. iommus = <&smmu arg1 arg2>, <&gart arg1 arg2>; Not yet ready for merge. Need to add iommus for other devices. Signed-off-by: Hiroshi Doyu --- v5: Use "iommus=" instead of "mmu-masters". Signed-off-by: Hiroshi Doyu --- arch/arm/boot/dts/tegra30.dtsi | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 2bd55cf..03b7887 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -1,6 +1,7 @@ #include #include #include +#include #include "skeleton.dtsi" @@ -92,6 +93,7 @@ interrupts = , /* syncpt */ ; /* general */ clocks = <&tegra_car TEGRA30_CLK_HOST1X>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(HC)>; #address-cells = <1>; #size-cells = <1>; @@ -103,6 +105,7 @@ reg = <0x54040000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_MPE>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(MPE)>; }; vi { @@ -110,6 +113,7 @@ reg = <0x54080000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_VI>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(VI)>; }; epp { @@ -117,6 +121,7 @@ reg = <0x540c0000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_EPP>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(EPP)>; }; isp { @@ -124,6 +129,7 @@ reg = <0x54100000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_ISP>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(ISP)>; }; gr2d { @@ -131,6 +137,7 @@ reg = <0x54140000 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_GR2D>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(G2)>; }; gr3d { @@ -139,6 +146,8 @@ clocks = <&tegra_car TEGRA30_CLK_GR3D &tegra_car TEGRA30_CLK_GR3D2>; clock-names = "3d", "3d2"; + iommus = <&smmu TEGRA_SWGROUP_CELLS(NV) + TEGRA_SWGROUP_CELLS(NV2)>; }; dc@54200000 { @@ -148,6 +157,7 @@ clocks = <&tegra_car TEGRA30_CLK_DISP1>, <&tegra_car TEGRA30_CLK_PLL_P>; clock-names = "disp1", "parent"; + iommus = <&smmu TEGRA_SWGROUP_CELLS(DC)>; rgb { status = "disabled"; @@ -161,6 +171,7 @@ clocks = <&tegra_car TEGRA30_CLK_DISP2>, <&tegra_car TEGRA30_CLK_PLL_P>; clock-names = "disp2", "parent"; + iommus = <&smmu TEGRA_SWGROUP_CELLS(DCB)>; rgb { status = "disabled"; @@ -317,6 +328,7 @@ interrupts = ; nvidia,dma-request-selector = <&apbdma 8>; clocks = <&tegra_car TEGRA30_CLK_UARTA>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS)>; status = "disabled"; }; @@ -327,6 +339,7 @@ interrupts = ; nvidia,dma-request-selector = <&apbdma 9>; clocks = <&tegra_car TEGRA30_CLK_UARTB>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS)>; status = "disabled"; }; @@ -337,6 +350,7 @@ interrupts = ; nvidia,dma-request-selector = <&apbdma 10>; clocks = <&tegra_car TEGRA30_CLK_UARTC>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS)>; status = "disabled"; }; @@ -347,6 +361,7 @@ interrupts = ; nvidia,dma-request-selector = <&apbdma 19>; clocks = <&tegra_car TEGRA30_CLK_UARTD>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS)>; status = "disabled"; }; @@ -357,6 +372,7 @@ interrupts = ; nvidia,dma-request-selector = <&apbdma 20>; clocks = <&tegra_car TEGRA30_CLK_UARTE>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS)>; status = "disabled"; }; @@ -525,7 +541,7 @@ interrupts = ; }; - iommu { + smmu: iommu { compatible = "nvidia,tegra30-smmu"; reg = <0x7000f010 0x02c 0x7000f1f0 0x010 @@ -533,6 +549,7 @@ nvidia,#asids = <4>; /* # of ASIDs */ dma-window = <0 0x40000000>; /* IOVA start & length */ nvidia,ahb = <&ahb>; + #iommu-cells = <2>; }; ahub { @@ -605,6 +622,7 @@ reg = <0x78000000 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS)>; status = "disabled"; }; @@ -613,6 +631,7 @@ reg = <0x78000200 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS)>; status = "disabled"; }; @@ -621,6 +640,7 @@ reg = <0x78000400 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS)>; status = "disabled"; }; @@ -629,6 +649,7 @@ reg = <0x78000600 0x200>; interrupts = ; clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; + iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS)>; status = "disabled"; };