From patchwork Fri Nov 22 23:57:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 3224601 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 8CC769F461 for ; Fri, 22 Nov 2013 23:57:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A4703205E4 for ; Fri, 22 Nov 2013 23:57:53 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 88DE7204D1 for ; Fri, 22 Nov 2013 23:57:52 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vk0aq-0002EF-7L; Fri, 22 Nov 2013 23:57:00 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vk0ac-0007nH-Ec; Fri, 22 Nov 2013 23:56:46 +0000 Received: from mail-pd0-f180.google.com ([209.85.192.180]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vk0aJ-0007l6-2F for linux-arm-kernel@lists.infradead.org; Fri, 22 Nov 2013 23:56:27 +0000 Received: by mail-pd0-f180.google.com with SMTP id q10so1891097pdj.39 for ; Fri, 22 Nov 2013 15:56:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qh5zEf4qCsOPP1suqAtJySwmPnw/JaC6eNQ08Qa4aNc=; b=lLpgKBlqQy+mbm5uFIbglv8Iwxgn64sVXy8CImoQJM21mFT9ROUvqTFVKua9bg3i+T G2Ts874WTxx2K4X6KnA1JQP6l007h0KArt1DTEKxKa4y7vobeN27Q14/YoqrSSX9RHSa 29Q4WycqMk9T3GLA9d8Z1F2CroByAZKnsv4JnhHg2YNHBkvmxEMp4F2AWeYIoEIm5HNd 3uyCmeCZpyzOGQASuEdOR6zZ7Y1DyGDQPktBoKQFqK0MSkYehgVS0bN7VMt/cdDmsYUf BldkpuJPBezgFyvUO3i01xkLYiTHiYImq4CttzJRMiFyiZ0/rtDelM0qcEgEo1BsOswJ XyaA== X-Gm-Message-State: ALoCoQmxedSQrsozmgnDa+UkAoWg8CkzHN+JJfSVHm2QZD/IcjGe3/KEVko9Oc8qdr4Fz7V4OLnW X-Received: by 10.66.182.199 with SMTP id eg7mr14692846pac.135.1385164565751; Fri, 22 Nov 2013 15:56:05 -0800 (PST) Received: from localhost.localdomain (c-67-169-181-221.hsd1.ca.comcast.net. [67.169.181.221]) by mx.google.com with ESMTPSA id sd3sm55895043pbb.42.2013.11.22.15.56.04 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 22 Nov 2013 15:56:05 -0800 (PST) From: Christoffer Dall To: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] arm/arm64: KVM: vgic: Use non-atomic bitops Date: Fri, 22 Nov 2013 15:57:19 -0800 Message-Id: <1385164639-18710-4-git-send-email-christoffer.dall@linaro.org> X-Mailer: git-send-email 1.8.4.3 In-Reply-To: <1385164639-18710-1-git-send-email-christoffer.dall@linaro.org> References: <1385164639-18710-1-git-send-email-christoffer.dall@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131122_185627_280039_904C21A7 X-CRM114-Status: GOOD ( 11.27 ) X-Spam-Score: -1.9 (-) Cc: Christoffer Dall X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Change the use of atomic bitops to use the non-atomic versions. All these operations are protected under a spinlock so using atomic operations is simply a waste of cycles. The test_and_clear_bit operations saves us ~500 cycles per world switch on TC2 on average. Changing the remaining bitops to their non-atomic versions saves us ~50 cycles over 100 repetitions of the average world-switch time of ~120,000 worls switches. Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic.c | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index ecee766..8f52d41 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -128,9 +128,9 @@ static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid, } if (val) - set_bit(irq, reg); + __set_bit(irq, reg); else - clear_bit(irq, reg); + __clear_bit(irq, reg); } static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid) @@ -219,19 +219,19 @@ static void vgic_dist_irq_clear(struct kvm_vcpu *vcpu, int irq) static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq) { if (irq < VGIC_NR_PRIVATE_IRQS) - set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); + __set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); else - set_bit(irq - VGIC_NR_PRIVATE_IRQS, - vcpu->arch.vgic_cpu.pending_shared); + __set_bit(irq - VGIC_NR_PRIVATE_IRQS, + vcpu->arch.vgic_cpu.pending_shared); } static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq) { if (irq < VGIC_NR_PRIVATE_IRQS) - clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); + __clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu); else - clear_bit(irq - VGIC_NR_PRIVATE_IRQS, - vcpu->arch.vgic_cpu.pending_shared); + __clear_bit(irq - VGIC_NR_PRIVATE_IRQS, + vcpu->arch.vgic_cpu.pending_shared); } static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask) @@ -466,9 +466,9 @@ static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq) kvm_for_each_vcpu(c, vcpu, kvm) { bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]); if (c == target) - set_bit(irq + i, bmap); + __set_bit(irq + i, bmap); else - clear_bit(irq + i, bmap); + __clear_bit(irq + i, bmap); } } } @@ -812,14 +812,14 @@ static void vgic_update_state(struct kvm *kvm) int c; if (!dist->enabled) { - set_bit(0, &dist->irq_pending_on_cpu); + __set_bit(0, &dist->irq_pending_on_cpu); return; } kvm_for_each_vcpu(c, vcpu, kvm) { if (compute_pending_for_cpu(vcpu)) { pr_debug("CPU%d has pending interrupts\n", c); - set_bit(c, &dist->irq_pending_on_cpu); + __set_bit(c, &dist->irq_pending_on_cpu); } } } @@ -848,7 +848,7 @@ static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) if (!vgic_irq_is_enabled(vcpu, irq)) { vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; - clear_bit(lr, vgic_cpu->lr_used); + __clear_bit(lr, vgic_cpu->lr_used); vgic_cpu->vgic_lr[lr] &= ~GICH_LR_STATE; if (vgic_irq_is_active(vcpu, irq)) vgic_irq_clear_active(vcpu, irq); @@ -893,7 +893,7 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); vgic_cpu->vgic_lr[lr] = MK_LR_PEND(sgi_source_id, irq); vgic_cpu->vgic_irq_lr_map[irq] = lr; - set_bit(lr, vgic_cpu->lr_used); + __set_bit(lr, vgic_cpu->lr_used); if (!vgic_irq_is_edge(vcpu, irq)) vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI; @@ -912,7 +912,7 @@ static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq) for_each_set_bit(c, &sources, VGIC_MAX_CPUS) { if (vgic_queue_irq(vcpu, c, irq)) - clear_bit(c, &sources); + __clear_bit(c, &sources); } dist->irq_sgi_sources[vcpu_id][irq] = sources; @@ -920,7 +920,7 @@ static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq) /* * If the sources bitmap has been cleared it means that we * could queue all the SGIs onto link registers (see the - * clear_bit above), and therefore we are done with them in + * __clear_bit above), and therefore we are done with them in * our emulated gic and can get rid of them. */ if (!sources) { @@ -1003,7 +1003,7 @@ epilog: * us. Claim we don't have anything pending. We'll * adjust that if needed while exiting. */ - clear_bit(vcpu_id, &dist->irq_pending_on_cpu); + __clear_bit(vcpu_id, &dist->irq_pending_on_cpu); } } @@ -1040,7 +1040,7 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) * Despite being EOIed, the LR may not have * been marked as empty. */ - set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr); + __set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr); vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT; } } @@ -1069,7 +1069,7 @@ static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) vgic_cpu->nr_lr) { int irq; - if (!test_and_clear_bit(lr, vgic_cpu->lr_used)) + if (!__test_and_clear_bit(lr, vgic_cpu->lr_used)) continue; irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID; @@ -1082,7 +1082,7 @@ static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) pending = find_first_zero_bit((unsigned long *)vgic_cpu->vgic_elrsr, vgic_cpu->nr_lr); if (level_pending || pending < vgic_cpu->nr_lr) - set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu); + __set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu); } void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) @@ -1200,7 +1200,7 @@ static bool vgic_update_irq_state(struct kvm *kvm, int cpuid, if (level) { vgic_cpu_irq_set(vcpu, irq_num); - set_bit(cpuid, &dist->irq_pending_on_cpu); + __set_bit(cpuid, &dist->irq_pending_on_cpu); } out: