From patchwork Mon Dec 2 13:55:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 3265601 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9CEED9F374 for ; Mon, 2 Dec 2013 13:59:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 73CF62026F for ; Mon, 2 Dec 2013 13:59:46 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A4FBD20254 for ; Mon, 2 Dec 2013 13:59:41 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VnU1c-0001Em-0O; Mon, 02 Dec 2013 13:59:00 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VnU1O-0005wx-0q; Mon, 02 Dec 2013 13:58:46 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VnU1K-0005ur-Cv for linux-arm-kernel@lists.infradead.org; Mon, 02 Dec 2013 13:58:43 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 02 Dec 2013 05:58:33 -0800 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 02 Dec 2013 05:55:29 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 02 Dec 2013 05:55:29 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.327.1; Mon, 2 Dec 2013 05:58:19 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Mon, 02 Dec 2013 05:58:19 -0800 Received: from ldewangan-ubuntu.nvidia.com (dhcp-10-19-65-30.nvidia.com [10.19.65.30]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id rB2DwFDP026419; Mon, 2 Dec 2013 05:58:16 -0800 (PST) From: Laxman Dewangan To: , Subject: [PATCH 1/2] ARM: dts: tegra: Header file for pinctrl constants Date: Mon, 2 Dec 2013 19:25:01 +0530 Message-ID: <1385992502-12771-1-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131202_085842_587199_D56E85A9 X-CRM114-Status: GOOD ( 11.99 ) X-Spam-Score: -1.9 (-) Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux@arm.linux.org.uk, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, Laxman Dewangan , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Defines pincontrol constants to use from Tegra's DTS file for tegra pincontrol properties option. Signed-off-by: Laxman Dewangan --- include/dt-bindings/pinctrl/pinctrl-tegra.h | 65 +++++++++++++++++++++++++++ 1 files changed, 65 insertions(+), 0 deletions(-) create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h new file mode 100644 index 0000000..c2bfa3f --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h @@ -0,0 +1,65 @@ +/* + * This header provides constants for TEGRA pinctrl bindings. + * + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * Author: Laxman Dewangan + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H +#define _DT_BINDINGS_PINCTRL_TEGRA_H + +/* Input/output */ +#define TEGRA_PIN_OUTPUT 0 +#define TEGRA_PIN_INPUT 1 + +/* Pull up/down/normal */ +#define TEGRA_PIN_PUPD_NORMAL 0 +#define TEGRA_PIN_PUPD_PULL_DOWN 1 +#define TEGRA_PIN_PUPD_PULL_UP 2 + +/* Tristate/normal */ +#define TEGRA_PIN_NORMAL 0 +#define TEGRA_PIN_TRISTATE 1 + +/* Rcv Sel enable/disable */ +#define TEGRA_PIN_RCV_SEL_DISABLE 0 +#define TEGRA_PIN_RCV_SEL_ENABLE 1 + +/* Lock enable/disable */ +#define TEGRA_PIN_LOCK_DISABLE 0 +#define TEGRA_PIN_LOCK_ENABLE 1 + +/* Open drain enable/disable */ +#define TEGRA_PIN_OPEN_DRAIN_DISABLE 0 +#define TEGRA_PIN_OPEN_DRAIN_ENABLE 1 + +/* High speed mode */ +#define TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_DISABLE 0 +#define TEGRA_PIN_DRIVE_HIGH_SPEED_MODE_ENABLE 1 + +/* Schmitt enable/disable */ +#define TEGRA_PIN_DRIVE_SCHMITT_DISABLE 0 +#define TEGRA_PIN_DRIVE_SCHMITT_ENABLE 1 + +/* Low power mode */ +#define TEGRA_PIN_LP_DRIVE_DIV_8 0 +#define TEGRA_PIN_LP_DRIVE_DIV_4 1 +#define TEGRA_PIN_LP_DRIVE_DIV_2 2 +#define TEGRA_PIN_LP_DRIVE_DIV_1 3 + +#define TEGRA_PIN_SLEW_RATE_FASTEST 0 +#define TEGRA_PIN_SLEW_RATE_FAST 1 +#define TEGRA_PIN_SLEW_RATE_SLOW 2 +#define TEGRA_PIN_SLEW_RATE_SLOWEST 3 + +#endif