From patchwork Tue Dec 3 13:16:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 3275921 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E0DD3C0D4A for ; Tue, 3 Dec 2013 13:20:22 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 46C102026D for ; Tue, 3 Dec 2013 13:20:18 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0228020268 for ; Tue, 3 Dec 2013 13:20:17 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VnptC-0004sW-2o; Tue, 03 Dec 2013 13:19:46 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vnpt5-0003Wm-VC; Tue, 03 Dec 2013 13:19:39 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vnpsy-0003UI-CJ for linux-arm-kernel@lists.infradead.org; Tue, 03 Dec 2013 13:19:34 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 03 Dec 2013 05:18:53 -0800 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 03 Dec 2013 05:12:21 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 03 Dec 2013 05:12:21 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.327.1; Tue, 3 Dec 2013 05:18:57 -0800 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Tue, 03 Dec 2013 05:18:57 -0800 Received: from ldewangan-ubuntu.nvidia.com (dhcp-10-19-65-30.nvidia.com [10.19.65.30]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id rB3DIoLi015446; Tue, 3 Dec 2013 05:18:51 -0800 (PST) From: Laxman Dewangan To: , Subject: [PATCH V2 1/2] ARM: tegra: Add header file for pinctrl constants Date: Tue, 3 Dec 2013 18:46:06 +0530 Message-ID: <1386076567-14283-1-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131203_081932_541962_6046C94C X-CRM114-Status: GOOD ( 13.11 ) X-Spam-Score: -1.9 (-) Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux@arm.linux.org.uk, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, Laxman Dewangan , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This new header file defines pincontrol constants for Tegra to use from Tegra's DTS file for pincontrol properties option. Signed-off-by: Laxman Dewangan Reviewed-by: Thierry Reding --- Changes from V1: - Get rid of lots of macro and converge it to TEGRA_PIN_ENABLE/DISABLE. - Change macro name for PULL UP/DOWN/NONE. include/dt-bindings/pinctrl/pinctrl-tegra.h | 40 +++++++++++++++++++++++++++ 1 files changed, 40 insertions(+), 0 deletions(-) create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h new file mode 100644 index 0000000..e5f02f8 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h @@ -0,0 +1,40 @@ +/* + * This header provides constants for TEGRA pinctrl bindings. + * + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * Author: Laxman Dewangan + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H +#define _DT_BINDINGS_PINCTRL_TEGRA_H + +#define TEGRA_PIN_DISABLE 0 +#define TEGRA_PIN_ENABLE 1 + +/* Pull up/down/normal */ +#define TEGRA_PIN_PULL_NONE 0 +#define TEGRA_PIN_PULL_DOWN 1 +#define TEGRA_PIN_PULL_UP 2 + +/* Low power mode */ +#define TEGRA_PIN_LP_DRIVE_DIV_8 0 +#define TEGRA_PIN_LP_DRIVE_DIV_4 1 +#define TEGRA_PIN_LP_DRIVE_DIV_2 2 +#define TEGRA_PIN_LP_DRIVE_DIV_1 3 + +#define TEGRA_PIN_SLEW_RATE_FASTEST 0 +#define TEGRA_PIN_SLEW_RATE_FAST 1 +#define TEGRA_PIN_SLEW_RATE_SLOW 2 +#define TEGRA_PIN_SLEW_RATE_SLOWEST 3 + +#endif