From patchwork Tue Dec 3 16:41:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 3277811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 30948C0D4A for ; Tue, 3 Dec 2013 16:44:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 72D682037A for ; Tue, 3 Dec 2013 16:44:32 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 118CA203A9 for ; Tue, 3 Dec 2013 16:44:31 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vnt3o-0007rK-F3; Tue, 03 Dec 2013 16:42:57 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vnt3R-0001OV-6u; Tue, 03 Dec 2013 16:42:33 +0000 Received: from mail-pd0-f172.google.com ([209.85.192.172]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vnt3K-0001L2-Kr for linux-arm-kernel@lists.infradead.org; Tue, 03 Dec 2013 16:42:28 +0000 Received: by mail-pd0-f172.google.com with SMTP id g10so20419393pdj.31 for ; Tue, 03 Dec 2013 08:42:04 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+yzvVrr5xj0ZtK4YfbjeIwb0DqgWwmrqm/AeH5aN2J8=; b=lPUkVp3VF/BUBejiAlKQgTvIrYb/6NDDwLVaf+KvJFCh2qShVeeE2EE+gACRWvTwW9 gRcr3xsa1N5UzFcRwopxqNfbLKJ0D2Zj+p2uCjgbEk4lYElVTsvzaCTv4qj7LKHbKOlA 6KLwG5TLYA+weaVFGGcrFUA2DyeT1EXeUos40VtmYrTsO8I2cjdVIaUoB3mnSwKyKjcf PaUwgtnTF4woUfDhSyoVKUP2YVberHm3kAFbTjJo2I6qBM0jU9Amz03fTM7iimkGiNao XZGXS9oTQR7ySGI4cZOT+Sk8Yw4W4BNO9xkX12gTxelSnOT/70WyP6znbdZBzAP5+Z7O WIcg== X-Gm-Message-State: ALoCoQkVjSFcbvmIdmJgw9QwEGKvhQcF3qAxGtjD0OMQaRx4Jr5e5a7u0VdO6mfv7CkvpH5UKBIN X-Received: by 10.66.136.101 with SMTP id pz5mr56603753pab.118.1386088924819; Tue, 03 Dec 2013 08:42:04 -0800 (PST) Received: from localhost ([219.142.3.202]) by mx.google.com with ESMTPSA id sy10sm148916400pac.15.2013.12.03.08.41.56 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 03 Dec 2013 08:42:04 -0800 (PST) From: Hanjun Guo To: "Rafael J. Wysocki" , Catalin Marinas , Will Deacon , Russell King - ARM Linux , Daniel Lezcano Subject: [RFC part3 PATCH 1/2] clocksource / arch_timer: Use ACPI GTDT table to initialize arch timer Date: Wed, 4 Dec 2013 00:41:30 +0800 Message-Id: <1386088891-2917-2-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1386088891-2917-1-git-send-email-hanjun.guo@linaro.org> References: <1386088891-2917-1-git-send-email-hanjun.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131203_114226_916375_1CFCFE44 X-CRM114-Status: GOOD ( 19.35 ) X-Spam-Score: -1.9 (-) Cc: Mark Rutland , Matthew Garrett , linaro-kernel@lists.linaro.org, patches@linaro.org, Linus Walleij , Olof Johansson , linux-kernel@vger.kernel.org, Rob Herring , linaro-acpi@lists.linaro.org, linux-acpi@vger.kernel.org, Amit Daniel Kachhap , Jon Masters , Grant Likely , Bjorn Helgaas , linux-arm-kernel@lists.infradead.org, Hanjun Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ACPI GTDT (Generic Timer Description Table) contains information for arch timer initialization, this patch use this table to probe arm timer. GTDT table is used for ARM/ARM64 only, please refer to chapter 5.2.24 of ACPI 5.0 spec for detailed inforamtion Signed-off-by: Amit Daniel Kachhap Signed-off-by: Hanjun Guo --- drivers/clocksource/arm_arch_timer.c | 129 ++++++++++++++++++++++++++++++---- include/clocksource/arm_arch_timer.h | 7 +- 2 files changed, 120 insertions(+), 16 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 95fb944..c968041 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -632,20 +633,8 @@ static void __init arch_timer_common_init(void) arch_timer_arch_init(); } -static void __init arch_timer_init(struct device_node *np) +static void __init arch_timer_init(void) { - int i; - - if (arch_timers_present & ARCH_CP15_TIMER) { - pr_warn("arch_timer: multiple nodes in dt, skipping\n"); - return; - } - - arch_timers_present |= ARCH_CP15_TIMER; - for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) - arch_timer_ppi[i] = irq_of_parse_and_map(np, i); - arch_timer_detect_rate(NULL, np); - /* * If HYP mode is available, we know that the physical timer * has been configured to be accessible from PL1. Use it, so @@ -667,8 +656,118 @@ static void __init arch_timer_init(struct device_node *np) arch_timer_register(); arch_timer_common_init(); } -CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init); -CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init); + +static void __init arch_timer_of_init(struct device_node *np) +{ + int i; + + if (arch_timers_present & ARCH_CP15_TIMER) { + pr_warn("arch_timer: multiple nodes in dt, skipping\n"); + return; + } + + arch_timers_present |= ARCH_CP15_TIMER; + for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) + arch_timer_ppi[i] = irq_of_parse_and_map(np, i); + arch_timer_detect_rate(NULL, np); + + arch_timer_init(); +} +CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); +CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init); + +#ifdef CONFIG_ACPI +void __init arch_timer_acpi_init(void) +{ + struct acpi_table_gtdt *gtdt; + acpi_size tbl_size; + int trigger, polarity; + void __iomem *base = NULL; + + if (acpi_disabled) + return; + + if (arch_timers_present & ARCH_CP15_TIMER) { + pr_warn("arch_timer: already initialized, skipping\n"); + return; + } + + if (ACPI_FAILURE(acpi_get_table_with_size(ACPI_SIG_GTDT, 0, + (struct acpi_table_header **)>dt, &tbl_size))) { + pr_err("arch_timer: GTDT table not defined\n"); + return; + } + + arch_timers_present |= ARCH_CP15_TIMER; + + /* + * Get the timer frequency. Since there is no frequency info + * in the GTDT table, so we should read it from CNTFREG register + * or hard code here to wait for the new ACPI spec available. + */ + if (!gtdt->address) { + arch_timer_rate = arch_timer_get_cntfrq(); + } else { + base = ioremap(gtdt->address, CNTFRQ); + if (!base) { + pr_warn("arch_timer: unable to map arch timer base address\n"); + return; + } + + arch_timer_rate = readl_relaxed(base + CNTFRQ); + iounmap(base); + } + + if (!arch_timer_rate) { + /* Hard code here to set frequence ? */ + pr_warn("arch_timer: Could not get frequency from GTDT table or CNTFREG\n"); + } + + if (gtdt->secure_pl1_interrupt) { + trigger = (gtdt->secure_pl1_flags & ACPI_GTDT_INTERRUPT_MODE) ? + ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; + polarity = + (gtdt->secure_pl1_flags & ACPI_GTDT_INTERRUPT_POLARITY) + ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH; + arch_timer_ppi[0] = acpi_register_gsi(NULL, + gtdt->secure_pl1_interrupt, trigger, polarity); + } + if (gtdt->non_secure_pl1_interrupt) { + trigger = + (gtdt->non_secure_pl1_flags & ACPI_GTDT_INTERRUPT_MODE) + ? ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; + polarity = + (gtdt->non_secure_pl1_flags & ACPI_GTDT_INTERRUPT_POLARITY) + ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH; + arch_timer_ppi[1] = acpi_register_gsi(NULL, + gtdt->non_secure_pl1_interrupt, trigger, polarity); + } + if (gtdt->virtual_timer_interrupt) { + trigger = (gtdt->virtual_timer_flags & ACPI_GTDT_INTERRUPT_MODE) + ? ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; + polarity = + (gtdt->virtual_timer_flags & ACPI_GTDT_INTERRUPT_POLARITY) + ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH; + arch_timer_ppi[2] = acpi_register_gsi(NULL, + gtdt->virtual_timer_interrupt, trigger, polarity); + } + if (gtdt->non_secure_pl2_interrupt) { + trigger = + (gtdt->non_secure_pl2_flags & ACPI_GTDT_INTERRUPT_MODE) + ? ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; + polarity = + (gtdt->non_secure_pl2_flags & ACPI_GTDT_INTERRUPT_POLARITY) + ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH; + arch_timer_ppi[3] = acpi_register_gsi(NULL, + gtdt->non_secure_pl2_interrupt, trigger, polarity); + } + + early_acpi_os_unmap_memory(gtdt, tbl_size); + arch_timer_init(); +} +#else +void __init arch_timer_acpi_init(void) { return; }; +#endif static void __init arch_timer_mem_init(struct device_node *np) { diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h index 6d26b40..2654edf 100644 --- a/include/clocksource/arm_arch_timer.h +++ b/include/clocksource/arm_arch_timer.h @@ -48,7 +48,7 @@ enum arch_timer_reg { extern u32 arch_timer_get_rate(void); extern u64 (*arch_timer_read_counter)(void); extern struct timecounter *arch_timer_get_timecounter(void); - +extern void __init arch_timer_acpi_init(void); #else static inline u32 arch_timer_get_rate(void) @@ -66,6 +66,11 @@ static inline struct timecounter *arch_timer_get_timecounter(void) return NULL; } +static inline void arch_timer_acpi_init(void) +{ + return; +} + #endif #endif