From patchwork Thu Dec 5 17:14:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3289341 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 93039C0D4A for ; Thu, 5 Dec 2013 17:17:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 424B020220 for ; Thu, 5 Dec 2013 17:17:32 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 07E41201FA for ; Thu, 5 Dec 2013 17:17:31 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VocXw-0004Eh-FO; Thu, 05 Dec 2013 17:17:04 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VocXq-0006rx-IR; Thu, 05 Dec 2013 17:16:58 +0000 Received: from co1ehsobe003.messaging.microsoft.com ([216.32.180.186] helo=co1outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VocXb-0006pF-MY for linux-arm-kernel@lists.infradead.org; Thu, 05 Dec 2013 17:16:44 +0000 Received: from mail134-co1-R.bigfish.com (10.243.78.239) by CO1EHSOBE016.bigfish.com (10.243.66.79) with Microsoft SMTP Server id 14.1.225.22; Thu, 5 Dec 2013 17:16:23 +0000 Received: from mail134-co1 (localhost [127.0.0.1]) by mail134-co1-R.bigfish.com (Postfix) with ESMTP id 77D651802BE; Thu, 5 Dec 2013 17:16:23 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hz70kz1de098h8275bh1de097hz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah224fh1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received-SPF: pass (mail134-co1: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail134-co1 (localhost.localdomain [127.0.0.1]) by mail134-co1 (MessageSwitch) id 1386263781830225_15116; Thu, 5 Dec 2013 17:16:21 +0000 (UTC) Received: from CO1EHSMHS023.bigfish.com (unknown [10.243.78.228]) by mail134-co1.bigfish.com (Postfix) with ESMTP id BA4025E023A; Thu, 5 Dec 2013 17:16:21 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by CO1EHSMHS023.bigfish.com (10.243.66.33) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 5 Dec 2013 17:16:21 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Thu, 5 Dec 2013 09:04:28 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id rB5HGDB5029700; Thu, 5 Dec 2013 09:16:19 -0800 (PST) From: To: , , , , , , , , , Subject: [PATCHv4 2/4] clk: socfpga: Add a hook for SD/MMC driver to control CIU clock settings Date: Thu, 5 Dec 2013 11:14:35 -0600 Message-ID: <1386263677-7733-3-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1386263677-7733-1-git-send-email-dinguyen@altera.com> References: <1386263677-7733-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131205_121643_966352_4D420107 X-CRM114-Status: GOOD ( 11.66 ) X-Spam-Score: -2.6 (--) Cc: devicetree@vger.kernel.org, linux-mmc@vger.kernel.org, Dinh Nguyen , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen Populate the .prepare function in the clk-ops for the "sdmmc_clk" that represents the "ciu" clock for the SD/MMC driver. The prepare function will handle setting the correct clock-phase for the CIU clock of the SD/MMC IP. Re-use the "rockchip,rk2928-dw-mshc" binding as it is already defined and appropriate for the SOCFPGA platform as well. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c index 60cb2f5..01baf20 100644 --- a/drivers/clk/socfpga/clk.c +++ b/drivers/clk/socfpga/clk.c @@ -55,7 +55,13 @@ #define div_mask(width) ((1 << (width)) - 1) #define streq(a, b) (strcmp((a), (b)) == 0) +#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 +/* SDMMC Group for System Manager defines */ +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) + extern void __iomem *clk_mgr_base_addr; +extern void __iomem *sys_manager_base_addr; struct socfpga_clk { struct clk_gate hw; @@ -68,6 +74,22 @@ struct socfpga_clk { }; #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw) +static int sdmmc_ciuclk_prepare(struct clk_hw *hwclk) +{ + struct device_node *np; + u32 timing[2]; + u32 hs_timing; + + np = of_find_compatible_node(NULL, NULL, "rockchip,rk2928-dw-mshc"); + if (of_property_read_u32_array(np, "samsung,dw-mshc-sdr-timing", timing, 2)) { + pr_err("SDMMC: cannot find samsung,dw-mshc-sdr-timing!\n"); + return -ENODATA; + } + hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[1], timing[0]); + writel(hs_timing, sys_manager_base_addr + SYSMGR_SDMMCGRP_CTRL_OFFSET); + return 0; +} + static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, unsigned long parent_rate) { @@ -274,6 +296,9 @@ static void __init socfpga_gate_clk_init(struct device_node *node, socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; socfpga_clk->hw.bit_idx = clk_gate[1]; + if (streq(clk_name, "sdmmc_clk")) + gateclk_ops.prepare = sdmmc_ciuclk_prepare; + gateclk_ops.enable = clk_gate_ops.enable; gateclk_ops.disable = clk_gate_ops.disable; }