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Sat, 07 Dec 2013 00:57:30 +0900 (KST) Received: from localhost.localdomain ([107.108.83.245]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MXE003WB6Z2JY10@mmp2.samsung.com>; Sat, 07 Dec 2013 00:57:30 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 5/7] clk/samsung: add support for pll2550xx Date: Fri, 06 Dec 2013 21:26:29 +0530 Message-id: <1386345391-23482-6-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1386345391-23482-1-git-send-email-rahul.sharma@samsung.com> References: <1386345391-23482-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplkeLIzCtJLcpLzFFi42JZI2JSq/vq88Igg6XPjS0+nrrNajH/yDlW i++7vrBb9C64ymax6fE1VosZ5/cxWTydcJHNYtFWoMTCF/EWUxYdZrXoWMZosWrXH0aLHS2r WRx4PXbOusvucefaHjaPzUvqPfq2rGL0+LxJLoA1issmJTUnsyy1SN8ugSvj6b+rjAWHVCt2 3drK3sDYKN/FyMkhIWAisb29nRHCFpO4cG89G4gtJLCUUeL/k5ouRg6wmsebiroYuYDC0xkl fs95xwzhtDNJbNl3EqyZTUBXYvbBZ4wgDSICmRIbt+SC1DAL/GWUuLB1FztIXFjAWmLWIkOQ chYBVYmWjc+YQGxeAQ+JB59esEHsUpCYM8kGxOQU8JRY9iAA4hoPiS0P+9hBJkoInGKXuNVx kw1ijIDEt8mHWCBaZSU2HWCG+ERS4uCKGywTGIUXMDKsYhRNLUguKE5KLzLUK07MLS7NS9dL zs/dxAiMitP/nvXuYLx9wPoQYzLQuInMUqLJ+cCoyiuJNzQ2M7IwNTE1NjK3NCNNWEmcN+lh UpCQQHpiSWp2ampBalF8UWlOavEhRiYOTqkGxpMrN2WaRt93jfXcWFRWcHzhL5ui4t9eli/Z jXaKfFm+9OzF6Oy4ImXLRMEpzYUfzqisLiyNfzLBa8X/3KUrrrh1Tb9qlJ6ypF5tY0zFLds1 rGXCPzeeWRLaJdG2+IWH/OQb6gdfic09o6kyt/vZwcy5ga9DDWZO2X373vmMDXHunTd+Gtz6 fl2JpTgj0VCLuag4EQC3goYYoAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNIsWRmVeSWpSXmKPExsVy+t9jQd1XnxcGGdx+r2Hx8dRtVov5R86x Wnzf9YXdonfBVTaLTY+vsVrMOL+PyeLphItsFou2AiUWvoi3mLLoMKtFxzJGi1W7/jBa7GhZ zeLA67Fz1l12jzvX9rB5bF5S79G3ZRWjx+dNcgGsUQ2MNhmpiSmpRQqpecn5KZl56bZK3sHx zvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlAJyoplCXmlAKFAhKLi5X07TBNCA1x07WAaYzQ 9Q0JgusxMkADCWsYM57+u8pYcEi1YtetrewNjI3yXYwcHBICJhKPNxV1MXICmWISF+6tZ+ti 5OIQEpjOKPF7zjtmCKedSWLLvpOMIFVsAroSsw8+YwRpFhHIlNi4JRekhlngL6PEha272EHi wgLWErMWGYKUswioSrRsfMYEYvMKeEg8+PSCDWKvgsScSTYgJqeAp8SyBwEgFUJAFVse9rFP YORdwMiwilE0tSC5oDgpPddIrzgxt7g0L10vOT93EyM46p5J72Bc1WBxiFGAg1GJh5dj1YIg IdbEsuLK3EOMEhzMSiK8R+4sDBLiTUmsrEotyo8vKs1JLT7EmAx000RmKdHkfGBCyCuJNzQ2 MTc1NrU0sTAxsyRNWEmc92CrdaCQQHpiSWp2ampBahHMFiYOTqkGxqYDu+xeViZc87VJP96o fZjHaTmv47RfZfWbD36b2PJQ60xU54U7gizsUlceehjKmsu8PBwvWvL7Xd7KJ8lea8rn6ces 6v7g2FS9XHTBxG0nExOKp+7a8LH1zYEphjcDJxQ7Lz32TFrX68WLf9y+2U8zjJYVNIRt2VXr /3WrKuOEVXGzzLeF2yuxFGckGmoxFxUnAgB+6jR5/gIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131206_105745_813639_05403268 X-CRM114-Status: GOOD ( 14.39 ) X-Spam-Score: -7.1 (-------) Cc: kgene.kim@samsung.com, mturquette@linaro.org, pankaj.dubey@samsung.com, joshi@samsung.com, tomasz.figa@gmail.com, thomas.ab@samsung.com, yg1004.jang@samsung.com, r.sh.open@gmail.com, arun.kk@samsung.com, Rahul Sharma X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Pankaj Dubey exynos5260 use pll2520xx and it has different bitfields for P,M,S values as compared to pll2550xx. Support for pll2520xx is added here. Signed-off-by: Pankaj Dubey Signed-off-by: Rahul Sharma Signed-off-by: Arun Kumar K --- drivers/clk/samsung/clk-pll.c | 107 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 108 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index e8e8953..237a889 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -710,6 +710,107 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, return clk; } +/* + * PLL2550xx Clock Type + */ + +/* Maximum lock time can be 270 * PDIV cycles */ +#define PLL2550XX_LOCK_FACTOR (270) + +#define PLL2550XX_MDIV_MASK (0x3FF) +#define PLL2550XX_PDIV_MASK (0x3F) +#define PLL2550XX_SDIV_MASK (0x7) +#define PLL2550XX_LOCK_STAT_MASK (0x1) +#define PLL2550XX_MDIV_SHIFT (9) +#define PLL2550XX_PDIV_SHIFT (3) +#define PLL2550XX_SDIV_SHIFT (0) +#define PLL2550XX_LOCK_STAT_SHIFT (21) + +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, pll_con; + u64 fvco = parent_rate; + + pll_con = __raw_readl(pll->con_reg); + mdiv = (pll_con >> PLL2550XX_MDIV_SHIFT) & PLL2550XX_MDIV_MASK; + pdiv = (pll_con >> PLL2550XX_PDIV_SHIFT) & PLL2550XX_PDIV_MASK; + sdiv = (pll_con >> PLL2550XX_SDIV_SHIFT) & PLL2550XX_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) +{ + if ((mdiv != ((pll_con >> PLL2550XX_MDIV_SHIFT) & + PLL2550XX_MDIV_MASK)) || + (pdiv != ((pll_con >> PLL2550XX_PDIV_SHIFT) & + PLL2550XX_PDIV_MASK))) + return 1; + else + return 0; +} + +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 tmp; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + tmp = __raw_readl(pll->con_reg); + + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { + /* If only s change, change just s value only*/ + tmp &= ~(PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT); + tmp |= rate->sdiv << PLL2550XX_SDIV_SHIFT; + __raw_writel(tmp, pll->con_reg); + } else { + /* Set PLL lock time. */ + __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); + + /* Change PLL PMS values */ + tmp &= ~((PLL2550XX_MDIV_MASK << PLL2550XX_MDIV_SHIFT) | + (PLL2550XX_PDIV_MASK << PLL2550XX_PDIV_SHIFT) | + (PLL2550XX_SDIV_MASK << PLL2550XX_SDIV_SHIFT)); + tmp |= (rate->mdiv << PLL2550XX_MDIV_SHIFT) | + (rate->pdiv << PLL2550XX_PDIV_SHIFT) | + (rate->sdiv << PLL2550XX_SDIV_SHIFT); + __raw_writel(tmp, pll->con_reg); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK + << PLL2550XX_LOCK_STAT_SHIFT))); + } + + return 0; +} + +static const struct clk_ops samsung_pll2550xx_clk_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll2550xx_set_rate, +}; + +static const struct clk_ops samsung_pll2550xx_clk_min_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, struct samsung_pll_clock *pll_clk, void __iomem *base) @@ -787,6 +888,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_pll46xx_clk_ops; break; + case pll_2550xx: + if (!pll->rate_table) + init.ops = &samsung_pll2550xx_clk_min_ops; + else + init.ops = &samsung_pll2550xx_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 6c39030..e106470 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -25,6 +25,7 @@ enum samsung_pll_type { pll_4650c, pll_6552, pll_6553, + pll_2550xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \