From patchwork Mon Dec 9 10:33:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 3310241 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 534639F380 for ; Mon, 9 Dec 2013 10:37:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D1D97201FB for ; Mon, 9 Dec 2013 10:37:39 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 22A9F2011B for ; Mon, 9 Dec 2013 10:37:38 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VpyDV-00076v-Jm; Mon, 09 Dec 2013 10:37:33 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VpyDT-0002AV-7J; Mon, 09 Dec 2013 10:37:31 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VpyDP-00029a-BS for linux-arm-kernel@lists.infradead.org; Mon, 09 Dec 2013 10:37:28 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 09 Dec 2013 02:36:59 -0800 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 09 Dec 2013 02:30:12 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 09 Dec 2013 02:30:12 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.327.1; Mon, 9 Dec 2013 02:37:04 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Mon, 09 Dec 2013 02:37:04 -0800 Received: from ldewangan-ubuntu.nvidia.com (dhcp-10-19-65-30.nvidia.com [10.19.65.30]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id rB9AauQw003174; Mon, 9 Dec 2013 02:36:57 -0800 (PST) From: Laxman Dewangan To: Subject: [PATCH] ARM: tegra: add default pinctrl nodes for Venice2 Date: Mon, 9 Dec 2013 16:03:51 +0530 Message-ID: <1386585231-1183-1-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131209_053727_651774_D89FD250 X-CRM114-Status: UNSURE ( 9.58 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.0 (--) Cc: devicetree@vger.kernel.org, linux@arm.linux.org.uk, linux-kernel@vger.kernel.org, thierry.reding@gmail.com, Laxman Dewangan , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan --- This change depends on the series of - adding dt-binding header file for pincontrol. The pinmux configuration is based on http://p4viewer/get///syseng/WMP/Projects/T124/ChromeBook/PM371/Venice2_T124_customer_pinmux_based_on_P4_rev47_2013-07-12.xlsm and downstream conifguration of pins for given SFIO. This is based o arch/arm/boot/dts/tegra124-venice2.dts | 376 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/tegra124.dtsi | 1 + 2 files changed, 377 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 431d67a..3a93a02 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -10,6 +10,382 @@ reg = <0x80000000 0x80000000>; }; + pinmux: pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: common { + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4", + "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0"; + nvidia,function = "cldvfs"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + dvfs_clk_px2 { + nvidia,pins = "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + + + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + + + pg4 { + nvidia,pins = "pg4", + "pg5", + "pg6", + "pg7", + "pi3"; + nvidia,function = "spi4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + ph0 { + nvidia,pins = "ph0"; + nvidia,function = "pwm0"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0", + "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,open-drain = ; + }; + + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + dap4_din_pp5 { + nvidia,pins = "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_fs_pp4", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5", + "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + + pu0 { + nvidia,pins = "pu0", + "pu1", + "pu2", + "pu3"; + nvidia,function = "uarta"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + uart2_cts_n_pj5 { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rts_n_pc0", + "uart3_rxd_pw7", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,open-drain = ; + }; + + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + }; + + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "usb"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + + usb_vbus_en1_pn5 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,enable-input = ; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,lock = ; + nvidia,open-drain = ; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <32>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + + drive_gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,low-power-mode = ; + nvidia,pull-down-strength = <1>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + nvidia,drive-type = <1>; + }; + }; + }; + serial@70006000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 05b9c0c..690c2d7 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1,4 +1,5 @@ #include +#include #include #include "skeleton.dtsi"