From patchwork Mon Dec 9 15:16:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Jensen X-Patchwork-Id: 3311601 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F0D6AC0D4A for ; Mon, 9 Dec 2013 15:17:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 346942018C for ; Mon, 9 Dec 2013 15:17:28 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C51E82016C for ; Mon, 9 Dec 2013 15:17:26 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vq2aF-0003Rq-Ny; Mon, 09 Dec 2013 15:17:19 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vq2aD-0007wo-Cz; Mon, 09 Dec 2013 15:17:17 +0000 Received: from mail-la0-x234.google.com ([2a00:1450:4010:c03::234]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vq2a9-0007vk-8a for linux-arm-kernel@lists.infradead.org; Mon, 09 Dec 2013 15:17:14 +0000 Received: by mail-la0-f52.google.com with SMTP id y1so1632701lam.25 for ; Mon, 09 Dec 2013 07:16:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7Z0QSIC+5KzVHToZTrW8z0l8eHjjnD86s7k4E1s6IqA=; b=je6Lr9rhfaH/iP5XpBhjDEc4ktcMrSZ64qnB06A1M27uc0hVBvml6SRyfXdzk10j1c jA657nIMlzJjaMOGl9pYQSV+GkWI7oz+862izwpm1h/R/MN5lOUJ44B0P5hKzC/mkdte R3jST5heLK4cYycRA90cQtXOHvTjlfjJ2CZnBHzoZarNlGy82o1WQmlnKpL0kXcJLYry ISWChLMfd21zhdlJ6mWQYFZvV0orJXtL2cUqUlEnj6qXrd1AutwOIoKjhJ2V3odFtIwV cLNWHLz5KvuHo/VVNzL+D/1UPta8RtCFoD323xZRp7Uo8VAXyvIZcmjyCXfjKOaByAd9 ALIA== X-Received: by 10.152.2.5 with SMTP id 5mr5552882laq.21.1386602211140; Mon, 09 Dec 2013 07:16:51 -0800 (PST) Received: from Ildjarn.ath.cx (static-213-115-41-10.sme.bredbandsbolaget.se. [213.115.41.10]) by mx.google.com with ESMTPSA id e10sm15151604laa.6.2013.12.09.07.16.49 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 09 Dec 2013 07:16:50 -0800 (PST) From: Jonas Jensen To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v8] clk: add MOXA ART SoCs clock driver Date: Mon, 9 Dec 2013 16:16:03 +0100 Message-Id: <1386602163-28479-1-git-send-email-jonas.jensen@gmail.com> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1381330482-13846-1-git-send-email-jonas.jensen@gmail.com> References: <1381330482-13846-1-git-send-email-jonas.jensen@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131209_101713_615485_57BE9340 X-CRM114-Status: GOOD ( 14.55 ) X-Spam-Score: -2.0 (--) Cc: mark.rutland@arm.com, adam.jaremko@gmail.com, mturquette@linaro.org, linux-kernel@vger.kernel.org, tomasz.figa@gmail.com, arm@kernel.org, sylvester.nawrocki@gmail.com, Jonas Jensen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds MOXA ART SoCs clock driver support. Signed-off-by: Jonas Jensen --- Notes: Thanks for the replies. As indicated by Sylwester, that it's discouraged to use hardware to register DT properties (multiplier-* divisor-*), I decided to remove them. They were only added as extra safety in cases where the implementation must be changed. Code readability is better of without them, and when something needs to change, it's probably better to do it directly. Changes since v7: 1. remove hardware to register properties (multiplier-* divisor-*) 2. remove redundant parentheses 3. check clk_register_fixed_rate() return value Applies to next-20131209 .../bindings/clock/moxa,moxart-clock.txt | 37 +++++++ drivers/clk/Makefile | 1 + drivers/clk/clk-moxart.c | 112 +++++++++++++++++++++ 3 files changed, 150 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt create mode 100644 drivers/clk/clk-moxart.c diff --git a/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt b/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt new file mode 100644 index 0000000..bc59ceb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt @@ -0,0 +1,37 @@ +Device Tree Clock bindings for arch-moxart + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +MOXA ART SoCs allow to determine PLL output and APB frequencies +by reading registers holding multiplier and divisor information. + +Required properties: +- compatible : Must be "moxa,moxart-pll-clock" or "moxa,moxart-apb-clock" +- #clock-cells : Should be 0 +- reg : Should contain registers location and length +- clocks : Should contain phandle to parent clock + +Optional properties for "moxa,moxart-pll-clock": +- clock-output-names : Should contain clock name + +Optional properties for "moxa,moxart-apb-clock": +- clock-output-names : Should contain clock name + + +For example: + + clk_pll: clk_pll@98100000 { + compatible = "moxa,moxart-pll-clock"; + #clock-cells = <0>; + reg = <0x98100000 0x34>; + clocks = <&ref12>; + }; + + clk_apb: clk_apb@98100000 { + compatible = "moxa,moxart-apb-clock"; + #clock-cells = <0>; + reg = <0x98100000 0x34>; + clocks = <&pll0>; + }; diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index ace7309..f07eb3b 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-composite.o # SoCs specific obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o +obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o diff --git a/drivers/clk/clk-moxart.c b/drivers/clk/clk-moxart.c new file mode 100644 index 0000000..f0436a3 --- /dev/null +++ b/drivers/clk/clk-moxart.c @@ -0,0 +1,112 @@ +/* + * MOXA ART SoCs clock driver. + * + * Copyright (C) 2013 Jonas Jensen + * + * Jonas Jensen + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include + +void __init moxart_of_pll_clk_init(struct device_node *node) +{ + static void __iomem *base; + struct clk *clk, *ref_clk; + unsigned long rate; + unsigned int mul; + const char *name = node->name; + + of_property_read_string(node, "clock-output-names", &name); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: of_iomap failed\n", node->full_name); + return; + } + + mul = readl(base + 0x30) >> 3 & 0x3f; + iounmap(base); + + ref_clk = of_clk_get(node, 0); + if (IS_ERR(ref_clk)) { + pr_err("%s: of_clk_get failed\n", node->full_name); + return; + } + + rate = mul * clk_get_rate(ref_clk); + + clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); + if (IS_ERR(clk)) { + pr_err("%s: clk_register_fixed_rate failed\n", node->full_name); + return; + } + + clk_register_clkdev(clk, NULL, name); + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock", + moxart_of_pll_clk_init); + +void __init moxart_of_apb_clk_init(struct device_node *node) +{ + static void __iomem *base; + struct clk *clk, *pll_clk; + unsigned long rate; + unsigned int div, val; + const char *name = node->name; + + of_property_read_string(node, "clock-output-names", &name); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s: of_iomap failed\n", node->full_name); + return; + } + + val = readl(base + 0xc) >> 4 & 0x7; + iounmap(base); + + switch (val) { + case 1: + div = 3; + break; + case 2: + div = 4; + break; + case 3: + div = 6; + break; + case 4: + div = 8; + break; + default: + div = 2; + break; + } + + pll_clk = of_clk_get(node, 0); + if (IS_ERR(pll_clk)) { + pr_err("%s: of_clk_get failed\n", node->full_name); + return; + } + + rate = clk_get_rate(pll_clk) / (div * 2); + + clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); + if (IS_ERR(clk)) { + pr_err("%s: clk_register_fixed_rate failed\n", node->full_name); + return; + } + + clk_register_clkdev(clk, NULL, name); + of_clk_add_provider(node, of_clk_src_simple_get, clk); +} +CLK_OF_DECLARE(moxart_apb_clock, "moxa,moxart-apb-clock", + moxart_of_apb_clk_init);