From patchwork Mon Dec 9 19:30:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3312421 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 46B0BC0D4A for ; Mon, 9 Dec 2013 19:33:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DF13420170 for ; Mon, 9 Dec 2013 19:33:12 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B819E2016C for ; Mon, 9 Dec 2013 19:33:07 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vq6Zg-0002DD-Om; Mon, 09 Dec 2013 19:33:00 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vq6Ze-0007qw-EF; Mon, 09 Dec 2013 19:32:58 +0000 Received: from mail-db9lp0251.outbound.messaging.microsoft.com ([213.199.154.251] helo=db9outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vq6Zb-0007q6-5P for linux-arm-kernel@lists.infradead.org; Mon, 09 Dec 2013 19:32:56 +0000 Received: from mail16-db9-R.bigfish.com (10.174.16.250) by DB9EHSOBE025.bigfish.com (10.174.14.88) with Microsoft SMTP Server id 14.1.225.22; Mon, 9 Dec 2013 19:32:32 +0000 Received: from mail16-db9 (localhost [127.0.0.1]) by mail16-db9-R.bigfish.com (Postfix) with ESMTP id 7F3C01A01A8; Mon, 9 Dec 2013 19:32:32 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 8 X-BigFish: VS8(zzzz1f42h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah224fh1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h286p1155h) Received-SPF: pass (mail16-db9: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=dinguyen@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail16-db9 (localhost.localdomain [127.0.0.1]) by mail16-db9 (MessageSwitch) id 1386617550299521_23381; Mon, 9 Dec 2013 19:32:30 +0000 (UTC) Received: from DB9EHSMHS008.bigfish.com (unknown [10.174.16.249]) by mail16-db9.bigfish.com (Postfix) with ESMTP id 440D0260111; Mon, 9 Dec 2013 19:32:30 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by DB9EHSMHS008.bigfish.com (10.174.14.18) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 9 Dec 2013 19:32:29 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.327.1; Mon, 9 Dec 2013 11:20:33 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id e031hl74005086; Sun, 2 Jan 2000 17:43:48 -0800 (PST) From: To: , , , Subject: [PATCH] clk: socfpga: Map the clk manager base address in the clock driver Date: Mon, 9 Dec 2013 13:30:47 -0600 Message-ID: <1386617447-1260-1-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131209_143255_523353_3B3F9B9B X-CRM114-Status: GOOD ( 15.54 ) X-Spam-Score: -1.9 (-) Cc: Dinh Nguyen , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen The clk manager's base address was being mapped in SOCFPGA's arch code and being extern'ed out to the clock driver. This method is not correct, and the arch code was not really doing anything with that clk manager anyways. This patch moves the mapping of the clk manager's base address in the clock driver itself. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/socfpga.c | 4 ---- drivers/clk/socfpga/clk.c | 43 +++++++++++++++++++++++++-------------- 2 files changed, 28 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index dd0d49c..c43c281 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -29,7 +29,6 @@ void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE)); void __iomem *sys_manager_base_addr; void __iomem *rst_manager_base_addr; -void __iomem *clk_mgr_base_addr; unsigned long cpu1start_addr; static struct map_desc scu_io_desc __initdata = { @@ -78,9 +77,6 @@ void __init socfpga_sysmgr_init(void) np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); rst_manager_base_addr = of_iomap(np, 0); - - np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); - clk_mgr_base_addr = of_iomap(np, 0); } static void __init socfpga_init_irq(void) diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c index 81dd31a..d1bc773 100644 --- a/drivers/clk/socfpga/clk.c +++ b/drivers/clk/socfpga/clk.c @@ -22,6 +22,7 @@ #include #include #include +#include /* Clock Manager offsets */ #define CLKMGR_CTRL 0x0 @@ -55,12 +56,11 @@ #define div_mask(width) ((1 << (width)) - 1) #define streq(a, b) (strcmp((a), (b)) == 0) -extern void __iomem *clk_mgr_base_addr; - struct socfpga_clk { struct clk_gate hw; char *parent_name; char *clk_name; + void __iomem *clk_mgr_base_addr; u32 fixed_div; void __iomem *div_reg; u32 width; /* only valid if div_reg != 0 */ @@ -76,7 +76,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, unsigned long bypass; reg = readl(socfpgaclk->hw.reg); - bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS); + bypass = readl(socfpgaclk->hw.reg + CLKMGR_BYPASS); if (bypass & MAINPLL_BYPASS) return parent_rate; @@ -118,6 +118,7 @@ static __init struct clk *socfpga_clk_init(struct device_node *node, const char *clk_name = node->name; const char *parent_name; struct clk_init_data init; + struct device_node *clk_mgr_np; int rc; u32 fixed_div; @@ -129,7 +130,11 @@ static __init struct clk *socfpga_clk_init(struct device_node *node, if (WARN_ON(!socfpga_clk)) return NULL; - socfpga_clk->hw.reg = clk_mgr_base_addr + reg; + /* Map the clk manager register */ + clk_mgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); + socfpga_clk->hw.reg = of_iomap(clk_mgr_np, 0); + BUG_ON(!socfpga_clk->hw.reg); + socfpga_clk->hw.reg += reg; rc = of_property_read_u32(node, "fixed-divider", &fixed_div); if (rc) @@ -167,19 +172,20 @@ static __init struct clk *socfpga_clk_init(struct device_node *node, static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) { + struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk); u32 l4_src; u32 perpll_src; if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { - l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); + l4_src = readl(socfpgaclk->clk_mgr_base_addr + CLKMGR_L4SRC); return l4_src &= 0x1; } if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { - l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); + l4_src = readl(socfpgaclk->clk_mgr_base_addr + CLKMGR_L4SRC); return !!(l4_src & 2); } - perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); + perpll_src = readl(socfpgaclk->clk_mgr_base_addr + CLKMGR_PERPLL_SRC); if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) return perpll_src &= 0x3; if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) || @@ -193,20 +199,21 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent) { + struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk); u32 src_reg; if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { - src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); + src_reg = readl(socfpgaclk->clk_mgr_base_addr + CLKMGR_L4SRC); src_reg &= ~0x1; src_reg |= parent; - writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); + writel(src_reg, socfpgaclk->clk_mgr_base_addr + CLKMGR_L4SRC); } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { - src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); + src_reg = readl(socfpgaclk->clk_mgr_base_addr + CLKMGR_L4SRC); src_reg &= ~0x2; src_reg |= (parent << 1); - writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); + writel(src_reg, socfpgaclk->clk_mgr_base_addr + CLKMGR_L4SRC); } else { - src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); + src_reg = readl(socfpgaclk->clk_mgr_base_addr + CLKMGR_PERPLL_SRC); if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) { src_reg &= ~0x3; src_reg |= parent; @@ -218,7 +225,7 @@ static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent) src_reg &= ~0x30; src_reg |= (parent << 4); } - writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC); + writel(src_reg, socfpgaclk->clk_mgr_base_addr + CLKMGR_PERPLL_SRC); } return 0; @@ -261,6 +268,7 @@ static void __init socfpga_gate_clk_init(struct device_node *node, const char *clk_name = node->name; const char *parent_name[SOCFGPA_MAX_PARENTS]; struct clk_init_data init; + struct device_node *clk_mgr_np; int rc; int i = 0; @@ -268,12 +276,17 @@ static void __init socfpga_gate_clk_init(struct device_node *node, if (WARN_ON(!socfpga_clk)) return; + /* Map the clk manager register */ + clk_mgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); + socfpga_clk->clk_mgr_base_addr = of_iomap(clk_mgr_np, 0); + BUG_ON(!socfpga_clk->clk_mgr_base_addr); + rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); if (rc) clk_gate[0] = 0; if (clk_gate[0]) { - socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; + socfpga_clk->hw.reg = socfpga_clk->clk_mgr_base_addr + clk_gate[0]; socfpga_clk->hw.bit_idx = clk_gate[1]; gateclk_ops.enable = clk_gate_ops.enable; @@ -288,7 +301,7 @@ static void __init socfpga_gate_clk_init(struct device_node *node, rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); if (!rc) { - socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; + socfpga_clk->div_reg = socfpga_clk->clk_mgr_base_addr + div_reg[0]; socfpga_clk->shift = div_reg[1]; socfpga_clk->width = div_reg[2]; } else {