From patchwork Wed Dec 18 21:26:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 3369091 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 46FEE9F32E for ; Wed, 18 Dec 2013 09:29:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 258C3201B6 for ; Wed, 18 Dec 2013 09:29:30 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CFC0C2018C for ; Wed, 18 Dec 2013 09:29:28 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VtDRR-00078E-NA; Wed, 18 Dec 2013 09:29:21 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VtDRP-0008VC-8o; Wed, 18 Dec 2013 09:29:19 +0000 Received: from co9ehsobe003.messaging.microsoft.com ([207.46.163.26] helo=co9outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VtDRM-0008UI-NU for linux-arm-kernel@lists.infradead.org; Wed, 18 Dec 2013 09:29:17 +0000 Received: from mail135-co9-R.bigfish.com (10.236.132.243) by CO9EHSOBE032.bigfish.com (10.236.130.95) with Microsoft SMTP Server id 14.1.225.22; Wed, 18 Dec 2013 09:28:51 +0000 Received: from mail135-co9 (localhost [127.0.0.1]) by mail135-co9-R.bigfish.com (Postfix) with ESMTP id 86BECA4069B; Wed, 18 Dec 2013 09:28:51 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 6 X-BigFish: VS6(zz853kzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6h1082kzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received: from mail135-co9 (localhost.localdomain [127.0.0.1]) by mail135-co9 (MessageSwitch) id 1387358929336902_28028; Wed, 18 Dec 2013 09:28:49 +0000 (UTC) Received: from CO9EHSMHS022.bigfish.com (unknown [10.236.132.243]) by mail135-co9.bigfish.com (Postfix) with ESMTP id 43043900047; Wed, 18 Dec 2013 09:28:49 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS022.bigfish.com (10.236.130.32) with Microsoft SMTP Server (TLS) id 14.16.227.3; Wed, 18 Dec 2013 09:28:49 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP Server (TLS) id 14.3.158.2; Wed, 18 Dec 2013 09:28:48 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id rBI9Sh4l010412; Wed, 18 Dec 2013 02:28:45 -0700 From: Anson Huang To: , , Subject: [PATCH V3 1/2] ARM: imx: add vddsoc/pu setpoint info into dts Date: Wed, 18 Dec 2013 16:26:49 -0500 Message-ID: <1387402010-31749-1-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131218_042916_904645_1B6B9A53 X-CRM114-Status: GOOD ( 10.67 ) X-Spam-Score: -2.3 (--) Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, cpufreq@vger.kernel.org, linux-pm@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP i.MX6Q needs to update vddarm, vddsoc/pu regulators when cpu freq is changed, each setpoint has different voltage, so we need to pass vddarm, vddsoc/pu's freq-voltage info from dts together. Signed-off-by: Anson Huang --- .../devicetree/bindings/cpufreq/cpufreq-imx6.txt | 56 ++++++++++++++++++++ arch/arm/boot/dts/imx6q.dtsi | 7 +++ 2 files changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-imx6.txt diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6.txt new file mode 100644 index 0000000..cf1c5f7 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6.txt @@ -0,0 +1,56 @@ +i.MX6 cpufreq driver +------------------- + +i.MX6 SoC cpufreq driver for CPU frequency scaling. + +This binding doc defines properties that must be put in the /cpus/cpu@0 node, +please refer to Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt +for detail. + +Required properties: +- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt + for details. +- clocks: Specify clocks that need to be used when cpu frequency is scaled, + refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for + details. +- clock-names: List of clock input name strings sorted in the same order as the + clocks property, refer to Documentation/devicetree/bindings/clock/clock-bindings.txt + for details. +- xxx-supply: Input voltage supply regulator, refer to + Documentation/devicetree/bindings/regulator/regulator.txt for details. + arm-supply: vddarm input. + pu-supply: vddpu input. + soc-supply: vddsoc input. + +Optional properties: +- fsl,soc-operating-points: Specify vddsoc/pu voltage settings that must + go with cpu0's operating-points. +- clock-latency: Specify the possible maximum transition latency for clock, + in unit of nanoseconds. + +Examples: + + cpu@0 { + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 792000 1150000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks 104>, <&clks 6>, <&clks 16>, + <&clks 17>, <&clks 170>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index e7e8332..021e0cb 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -30,6 +30,13 @@ 792000 1150000 396000 975000 >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks 104>, <&clks 6>, <&clks 16>, <&clks 17>, <&clks 170>;