@@ -316,6 +316,12 @@
clock-names = "pclk", "clk32k_in";
};
+ efuse@7000f800 {
+ compatible = "nvidia,tegra114-efuse";
+ reg = <0x7000f800 0x400>;
+ clocks = <&tegra_car TEGRA114_CLK_FUSE>;
+ };
+
iommu {
compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
reg = <0x70019010 0x02c
@@ -106,6 +106,12 @@
reg = <0x7000e400 0x400>;
};
+ efuse@7000f800 {
+ compatible = "nvidia,tegra124-efuse";
+ reg = <0x7000f800 0x400>;
+ clocks = <&tegra_car TEGRA124_CLK_FUSE>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -121,6 +121,7 @@
};
};
+
timer@50004600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x50040600 0x20>;
@@ -455,6 +456,12 @@
#size-cells = <0>;
};
+ efuse@7000F800 {
+ compatible = "nvidia,tegra20-efuse";
+ reg = <0x7000F800 0x400>;
+ clocks = <&tegra_car TEGRA20_CLK_FUSE>;
+ };
+
pcie-controller {
compatible = "nvidia,tegra20-pcie";
device_type = "pci";
@@ -535,6 +535,12 @@
nvidia,ahb = <&ahb>;
};
+ efuse@7000f800 {
+ compatible = "nvidia,tegra30-efuse";
+ reg = <0x7000f800 0x400>;
+ clocks = <&tegra_car TEGRA30_CLK_FUSE>;
+ };
+
ahub {
compatible = "nvidia,tegra30-ahub";
reg = <0x70080000 0x200
Add efuse bindings for Tegra20, Tegra30, Tegra114 and Tegra124. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> --- arch/arm/boot/dts/tegra114.dtsi | 6 ++++++ arch/arm/boot/dts/tegra124.dtsi | 6 ++++++ arch/arm/boot/dts/tegra20.dtsi | 7 +++++++ arch/arm/boot/dts/tegra30.dtsi | 6 ++++++ 4 files changed, 25 insertions(+), 0 deletions(-)