From patchwork Mon Dec 23 18:10:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taras Kondratiuk X-Patchwork-Id: 3397801 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5068E9F169 for ; Mon, 23 Dec 2013 18:12:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6DB4C205F3 for ; Mon, 23 Dec 2013 18:12:07 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2993220591 for ; Mon, 23 Dec 2013 18:12:06 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vv9yd-0007kM-Jr; Mon, 23 Dec 2013 18:11:39 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vv9yU-000567-Fn; Mon, 23 Dec 2013 18:11:30 +0000 Received: from mail-ee0-f49.google.com ([74.125.83.49]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vv9yE-00053F-BT for linux-arm-kernel@lists.infradead.org; Mon, 23 Dec 2013 18:11:17 +0000 Received: by mail-ee0-f49.google.com with SMTP id c41so2472279eek.22 for ; Mon, 23 Dec 2013 10:10:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EWbZ+wqHUUsDsUMX32ohfdbo2N7DG08mR1CDo1DAl3k=; b=bnOqZe3P0f+yrPWew1xEgtp7LfUSXfedph/+ZXNzT1aDmK47DZKtGsKEiCCTKS9VIN 7+0B3sdyd2VBJZrbi26kYbVtiiKlBAkD3V2txPtak8d71RoHVb5DPkefPMj/6YfvV8ah aYAA9gV6T0yFA+7kHDQBq/S30bckXc9f1hv1C2OCkzJVzbPOMz3OYX0btQOqCdHfFRlj 2/Yi/MJCzxtHFa2ZVum+73S+1bd9kPKJXJCLtQ0w/YMXEIgRvJGZPpbn6JP7yfrAG+2Q RkD0RjgSsDIFHmJSLIx1636Ixzrtj5xJ1QYCv899whk9ot8hLWsQCrHg6BJDXIbVqN4D eCuQ== X-Gm-Message-State: ALoCoQnBa4u5aTw13kYiwektkjj/aARbqKgb9G2nrxuHW4jO8IiU0V+YIz+CC+NCFTvYCPGbDtCn X-Received: by 10.14.88.5 with SMTP id z5mr829680eee.101.1387822250362; Mon, 23 Dec 2013 10:10:50 -0800 (PST) Received: from condor-x220.synapse.com ([195.238.93.36]) by mx.google.com with ESMTPSA id o47sm47754698eem.21.2013.12.23.10.10.49 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 23 Dec 2013 10:10:50 -0800 (PST) From: Taras Kondratiuk To: Tony Lindgren Subject: [PATCH 2/4] ARM: OMAP: dmtimer: raw read and write endian fix Date: Mon, 23 Dec 2013 20:10:32 +0200 Message-Id: <1387822234-11167-3-git-send-email-taras.kondratiuk@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1387822234-11167-1-git-send-email-taras.kondratiuk@linaro.org> References: <1387822234-11167-1-git-send-email-taras.kondratiuk@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131223_131114_593454_09EFEE48 X-CRM114-Status: GOOD ( 15.63 ) X-Spam-Score: -2.6 (--) Cc: linaro-kernel@lists.linaro.org, Russell King , Victor Kamensky , Taras Kondratiuk , patches@linaro.org, linux-kernel@vger.kernel.org, linaro-networking@linaro.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Victor Kamensky All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- arch/arm/plat-omap/dmtimer.c | 8 ++++---- arch/arm/plat-omap/include/plat/dmtimer.h | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 869254c..db10169 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -103,7 +103,7 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer) timer->context.tmar); omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr); - __raw_writel(timer->context.tier, timer->irq_ena); + writel_relaxed(timer->context.tier, timer->irq_ena); omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr); } @@ -699,9 +699,9 @@ int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) omap_dm_timer_enable(timer); if (timer->revision == 1) - l = __raw_readl(timer->irq_ena) & ~mask; + l = readl_relaxed(timer->irq_ena) & ~mask; - __raw_writel(l, timer->irq_dis); + writel_relaxed(l, timer->irq_dis); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); @@ -722,7 +722,7 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) return 0; } - l = __raw_readl(timer->irq_stat); + l = readl_relaxed(timer->irq_stat); return l; } diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 2861b15..dd79f30 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -280,20 +280,20 @@ static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, int posted) { if (posted) - while (__raw_readl(timer->pend) & (reg >> WPSHIFT)) + while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) cpu_relax(); - return __raw_readl(timer->func_base + (reg & 0xff)); + return readl_relaxed(timer->func_base + (reg & 0xff)); } static inline void __omap_dm_timer_write(struct omap_dm_timer *timer, u32 reg, u32 val, int posted) { if (posted) - while (__raw_readl(timer->pend) & (reg >> WPSHIFT)) + while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) cpu_relax(); - __raw_writel(val, timer->func_base + (reg & 0xff)); + writel_relaxed(val, timer->func_base + (reg & 0xff)); } static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) @@ -301,7 +301,7 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) u32 tidr; /* Assume v1 ip if bits [31:16] are zero */ - tidr = __raw_readl(timer->io_base); + tidr = readl_relaxed(timer->io_base); if (!(tidr >> 16)) { timer->revision = 1; timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; @@ -385,7 +385,7 @@ static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer, } /* Ack possibly pending interrupt */ - __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat); + writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat); } static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer, @@ -399,7 +399,7 @@ static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer, static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer, unsigned int value) { - __raw_writel(value, timer->irq_ena); + writel_relaxed(value, timer->irq_ena); __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0); } @@ -412,7 +412,7 @@ __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted) static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) { - __raw_writel(value, timer->irq_stat); + writel_relaxed(value, timer->irq_stat); } #endif /* __ASM_ARCH_DMTIMER_H */