From patchwork Thu Jan 2 09:57:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiubo Li X-Patchwork-Id: 3424391 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 05D72C02DC for ; Thu, 2 Jan 2014 10:53:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 86ABA2015B for ; Thu, 2 Jan 2014 10:53:09 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8C51120149 for ; Thu, 2 Jan 2014 10:53:07 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VyftC-0007Rn-E8; Thu, 02 Jan 2014 10:52:34 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vyft1-0000a0-JG; Thu, 02 Jan 2014 10:52:23 +0000 Received: from mail-db8lp0188.outbound.messaging.microsoft.com ([213.199.154.188] helo=db8outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Vyfsx-0000YQ-R6 for linux-arm-kernel@lists.infradead.org; Thu, 02 Jan 2014 10:52:21 +0000 Received: from mail111-db8-R.bigfish.com (10.174.8.234) by DB8EHSOBE009.bigfish.com (10.174.4.72) with Microsoft SMTP Server id 14.1.225.22; Thu, 2 Jan 2014 10:51:55 +0000 Received: from mail111-db8 (localhost [127.0.0.1]) by mail111-db8-R.bigfish.com (Postfix) with ESMTP id A2DEE2C0232; Thu, 2 Jan 2014 10:51:55 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 4 X-BigFish: VS4(z551bizc8kzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh2a8h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received: from mail111-db8 (localhost.localdomain [127.0.0.1]) by mail111-db8 (MessageSwitch) id 1388659913935649_22349; Thu, 2 Jan 2014 10:51:53 +0000 (UTC) Received: from DB8EHSMHS015.bigfish.com (unknown [10.174.8.231]) by mail111-db8.bigfish.com (Postfix) with ESMTP id D2B29120047; Thu, 2 Jan 2014 10:51:53 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS015.bigfish.com (10.174.4.25) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 2 Jan 2014 10:51:53 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.3.158.2; Thu, 2 Jan 2014 10:51:52 +0000 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s02ApfUw019354; Thu, 2 Jan 2014 03:51:48 -0700 From: Xiubo Li To: , , Subject: [PATCHv8 1/4] pwm: Add Freescale FTM PWM driver support Date: Thu, 2 Jan 2014 17:57:01 +0800 Message-ID: <1388656624-26570-2-git-send-email-Li.Xiubo@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1388656624-26570-1-git-send-email-Li.Xiubo@freescale.com> References: <1388656624-26570-1-git-send-email-Li.Xiubo@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140102_055220_178879_D8A372AE X-CRM114-Status: GOOD ( 22.43 ) X-Spam-Score: -0.6 (/) Cc: linux-doc@vger.kernel.org, Alison Wang , linux-kernel@vger.kernel.org, Xiubo Li , Jingchang Lu , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD,UNPARSEABLE_RELAY,UNRESOLVED_TEMPLATE autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The FTM PWM device can be found on Vybrid VF610 Tower and Layerscape LS-1 SoCs. Signed-off-by: Xiubo Li Signed-off-by: Alison Wang Signed-off-by: Jingchang Lu Reviewed-by: Sascha Hauer --- drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-fsl-ftm.c | 514 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 525 insertions(+) create mode 100644 drivers/pwm/pwm-fsl-ftm.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 3f66427..ec4bf78 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -71,6 +71,16 @@ config PWM_EP93XX To compile this driver as a module, choose M here: the module will be called pwm-ep93xx. +config PWM_FSL_FTM + tristate "Freescale FlexTimer Module (FTM) PWM support" + depends on OF + help + Generic FTM PWM framework driver for Freescale VF610 and + Layerscape LS-1 SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-fsl-ftm. + config PWM_IMX tristate "i.MX PWM support" depends on ARCH_MXC diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 8b754e4..b335db1 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o +obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c new file mode 100644 index 0000000..c201e20 --- /dev/null +++ b/drivers/pwm/pwm-fsl-ftm.c @@ -0,0 +1,514 @@ +/* + * Freescale FlexTimer Module (FTM) PWM Driver + * + * Copyright 2012-2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FTM_SC 0x00 +#define FTM_SC_CLK_MASK 0x3 +#define FTM_SC_CLK_SHIFT 3 +#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_SHIFT) +#define FTM_SC_PS_MASK 0x7 +#define FTM_SC_PS_SHIFT 0 + +#define FTM_CNT 0x04 +#define FTM_MOD 0x08 + +#define FTM_CSC_BASE 0x0C +#define FTM_CSC_MSB BIT(5) +#define FTM_CSC_MSA BIT(4) +#define FTM_CSC_ELSB BIT(3) +#define FTM_CSC_ELSA BIT(2) +#define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8)) + +#define FTM_CV_BASE 0x10 +#define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8)) + +#define FTM_CNTIN 0x4C +#define FTM_STATUS 0x50 + +#define FTM_MODE 0x54 +#define FTM_MODE_FTMEN BIT(0) +#define FTM_MODE_INIT BIT(2) +#define FTM_MODE_PWMSYNC BIT(3) + +#define FTM_SYNC 0x58 +#define FTM_OUTINIT 0x5C +#define FTM_OUTMASK 0x60 +#define FTM_COMBINE 0x64 +#define FTM_DEADTIME 0x68 +#define FTM_EXTTRIG 0x6C +#define FTM_POL 0x70 +#define FTM_FMS 0x74 +#define FTM_FILTER 0x78 +#define FTM_FLTCTRL 0x7C +#define FTM_QDCTRL 0x80 +#define FTM_CONF 0x84 +#define FTM_FLTPOL 0x88 +#define FTM_SYNCONF 0x8C +#define FTM_INVCTRL 0x90 +#define FTM_SWOCTRL 0x94 +#define FTM_PWMLOAD 0x98 + +enum fsl_pwm_clk { + FSL_PWM_CLK_SYS, + FSL_PWM_CLK_FIX, + FSL_PWM_CLK_EXT, +}; + +struct fsl_pwm_chip { + struct pwm_chip chip; + + struct mutex lock; + + struct clk *sys_clk; + struct clk *counter_clk; + struct clk *counter_clk_en; + unsigned int counter_clk_select; + unsigned int counter_clk_enable; + unsigned int clk_ps; + + void __iomem *base; + + int period_ns; + bool big_endian; +}; + +static inline u32 ftm_readl(bool big_endian, const void __iomem *addr) +{ + u32 val; + + val = __raw_readl(addr); + + if (likely(big_endian)) + val = be32_to_cpu((__force __be32)val); + else + val = le32_to_cpu((__force __le32)val); + rmb(); + + return val; +} + +static inline void ftm_writel(bool big_endian, u32 val, void __iomem *addr) +{ + wmb(); + if (likely(big_endian)) + val = (__force u32)cpu_to_be32(val); + else + val = (__force u32)cpu_to_le32(val); + + __raw_writel(val, addr); +} + +static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct fsl_pwm_chip, chip); +} + +static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct fsl_pwm_chip *fpc = to_fsl_chip(chip); + + return clk_prepare_enable(fpc->sys_clk); +} + +static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct fsl_pwm_chip *fpc = to_fsl_chip(chip); + + clk_disable_unprepare(fpc->sys_clk); +} + +static inline int +fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc, enum fsl_pwm_clk index) +{ + unsigned long sys_rate, cnt_rate; + unsigned long long ratio; + + sys_rate = clk_get_rate(fpc->sys_clk); + if (!sys_rate) + return -EINVAL; + + cnt_rate = clk_get_rate(fpc->counter_clk); + if (!cnt_rate) + return -EINVAL; + + switch (index) { + case FSL_PWM_CLK_SYS: + fpc->clk_ps = 1; + break; + case FSL_PWM_CLK_FIX: + ratio = 2 * cnt_rate - 1; + do_div(ratio, sys_rate); + fpc->clk_ps = ratio; + break; + case FSL_PWM_CLK_EXT: + ratio = 4 * cnt_rate - 1; + do_div(ratio, sys_rate); + fpc->clk_ps = ratio; + break; + } + + return 0; +} + +static inline unsigned long +fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc, unsigned long period_ns) +{ + unsigned long long c, c0; + + c = clk_get_rate(fpc->counter_clk); + c = c * period_ns; + do_div(c, 1000000000UL); + + do { + c0 = c; + do_div(c0, (1 << fpc->clk_ps)); + if (c0 <= 0xFFFF) + return (unsigned long)c0; + } while (++fpc->clk_ps < 8); + + return 0; +} + +static unsigned long +fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc, + unsigned long period_ns, + enum fsl_pwm_clk index) +{ + int ret; + + fpc->counter_clk_select = FTM_SC_CLK(index); + + ret = fsl_pwm_calculate_default_ps(fpc, index); + if (ret) { + dev_err(fpc->chip.dev, "failed to calculate default " + "prescaler: %d\n", ret); + return 0; + } + + return fsl_pwm_calculate_cycles(fpc, period_ns); +} + +static unsigned long +fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc, unsigned long period_ns) +{ + struct clk *cnt_clk[3]; + enum fsl_pwm_clk m0, m1; + unsigned long fix_rate, ext_rate, cycles; + + fpc->counter_clk = fpc->sys_clk; + cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, + FSL_PWM_CLK_SYS); + if (cycles) + return cycles; + + cnt_clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix"); + if (IS_ERR(cnt_clk[FSL_PWM_CLK_FIX])) + return PTR_ERR(cnt_clk[FSL_PWM_CLK_FIX]); + + cnt_clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext"); + if (IS_ERR(cnt_clk[FSL_PWM_CLK_EXT])) + return PTR_ERR(cnt_clk[FSL_PWM_CLK_EXT]); + + fpc->counter_clk_en = devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en"); + if (IS_ERR(fpc->counter_clk_en)) + return PTR_ERR(fpc->counter_clk_en); + + fix_rate = clk_get_rate(cnt_clk[FSL_PWM_CLK_FIX]); + ext_rate = clk_get_rate(cnt_clk[FSL_PWM_CLK_EXT]); + + if (fix_rate > ext_rate) { + m0 = FSL_PWM_CLK_FIX; + m1 = FSL_PWM_CLK_EXT; + } else { + m0 = FSL_PWM_CLK_EXT; + m1 = FSL_PWM_CLK_FIX; + } + + fpc->counter_clk = cnt_clk[m0]; + cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0); + if (cycles) + return cycles; + + fpc->counter_clk = cnt_clk[m1]; + + return fsl_pwm_calculate_period_cycles(fpc, period_ns, m0); +} + +static unsigned long +fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc, + unsigned long period_ns, + unsigned long duty_ns) +{ + unsigned long long val, duty; + + val = ftm_readl(fpc->big_endian, fpc->base + FTM_MOD); + duty = duty_ns * (val + 1); + do_div(duty, period_ns); + + return (unsigned long)duty; +} + +static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) +{ + struct fsl_pwm_chip *fpc = to_fsl_chip(chip); + u32 val, period, duty; + + mutex_lock(&fpc->lock); + + /* + * The Freescale FTM controller supports only a single period for + * all PWM channels, therefore incompatible changes need to be + * refused. + */ + if (fpc->period_ns && fpc->period_ns != period_ns) { + dev_err(fpc->chip.dev, + "conflicting period requested for PWM %u\n", + pwm->hwpwm); + mutex_unlock(&fpc->lock); + return -EBUSY; + } + + if (!fpc->period_ns && duty_ns) { + period = fsl_pwm_calculate_period(fpc, period_ns); + if (!period) { + dev_err(fpc->chip.dev, "failed to calculate period\n"); + mutex_unlock(&fpc->lock); + return -EINVAL; + } + + val = ftm_readl(fpc->big_endian, fpc->base + FTM_SC); + val &= ~(FTM_SC_PS_MASK << FTM_SC_PS_SHIFT); + val |= fpc->clk_ps; + ftm_writel(fpc->big_endian, val, fpc->base + FTM_SC); + ftm_writel(fpc->big_endian, period - 1, fpc->base + FTM_MOD); + + fpc->period_ns = period_ns; + } + + mutex_unlock(&fpc->lock); + + duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns); + + ftm_writel(fpc->big_endian, FTM_CSC_MSB | FTM_CSC_ELSB, + fpc->base + FTM_CSC(pwm->hwpwm)); + ftm_writel(fpc->big_endian, duty, fpc->base + FTM_CV(pwm->hwpwm)); + + return 0; +} + +static int fsl_pwm_set_polarity(struct pwm_chip *chip, + struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + struct fsl_pwm_chip *fpc = to_fsl_chip(chip); + u32 val; + + val = ftm_readl(fpc->big_endian, fpc->base + FTM_POL); + + if (polarity == PWM_POLARITY_INVERSED) + val |= BIT(pwm->hwpwm); + else + val &= ~BIT(pwm->hwpwm); + + ftm_writel(fpc->big_endian, val, fpc->base + FTM_POL); + + return 0; +} + +static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc) +{ + u32 val; + int ret; + + if (fpc->counter_clk_enable++) + return 0; + + ret = clk_prepare_enable(fpc->counter_clk); + if (ret) { + fpc->counter_clk_enable--; + return ret; + } + + ret = clk_prepare_enable(fpc->counter_clk_en); + if (ret) { + fpc->counter_clk_enable--; + return ret; + } + + /* select counter clock source */ + val = ftm_readl(fpc->big_endian, fpc->base + FTM_SC); + val &= ~(FTM_SC_CLK_MASK << FTM_SC_CLK_SHIFT); + val |= fpc->counter_clk_select; + ftm_writel(fpc->big_endian, val, fpc->base + FTM_SC); + + return 0; +} + +static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct fsl_pwm_chip *fpc = to_fsl_chip(chip); + u32 val; + int ret; + + val = ftm_readl(fpc->big_endian, fpc->base + FTM_OUTMASK); + val &= ~BIT(pwm->hwpwm); + ftm_writel(fpc->big_endian, val, fpc->base + FTM_OUTMASK); + + mutex_lock(&fpc->lock); + ret = fsl_counter_clock_enable(fpc); + mutex_unlock(&fpc->lock); + + return ret; +} + +static inline void fsl_counter_clock_disable(struct fsl_pwm_chip *fpc) +{ + u32 val; + + if (--fpc->counter_clk_enable) + return; + + val = ftm_readl(fpc->big_endian, fpc->base + FTM_SC); + val &= ~(FTM_SC_CLK_MASK << FTM_SC_CLK_SHIFT); + ftm_writel(fpc->big_endian, val, fpc->base + FTM_SC); + + clk_disable_unprepare(fpc->counter_clk_en); + clk_disable_unprepare(fpc->counter_clk); +} + +static void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct fsl_pwm_chip *fpc = to_fsl_chip(chip); + u32 val; + + val = ftm_readl(fpc->big_endian, fpc->base + FTM_OUTMASK); + val |= BIT(pwm->hwpwm); + ftm_writel(fpc->big_endian, val, fpc->base + FTM_OUTMASK); + + mutex_lock(&fpc->lock); + + fsl_counter_clock_disable(fpc); + + val = ftm_readl(fpc->big_endian, fpc->base + FTM_OUTMASK); + + if ((val & 0xFF) == 0xFF) { + fpc->period_ns = 0; + fpc->counter_clk_en = NULL; + } + + mutex_unlock(&fpc->lock); +} + +static const struct pwm_ops fsl_pwm_ops = { + .request = fsl_pwm_request, + .free = fsl_pwm_free, + .config = fsl_pwm_config, + .set_polarity = fsl_pwm_set_polarity, + .enable = fsl_pwm_enable, + .disable = fsl_pwm_disable, + .owner = THIS_MODULE, +}; + +static int fsl_pwm_probe(struct platform_device *pdev) +{ + struct fsl_pwm_chip *fpc; + struct resource *res; + struct device_node *np = pdev->dev.of_node; + int ret; + + fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL); + if (!fpc) + return -ENOMEM; + + mutex_init(&fpc->lock); + + fpc->chip.dev = &pdev->dev; + + fpc->big_endian = of_property_read_bool(np, "big-endian"); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + fpc->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(fpc->base)) + return PTR_ERR(fpc->base); + + fpc->sys_clk = devm_clk_get(&pdev->dev, "ftm_sys"); + if (IS_ERR(fpc->sys_clk)) { + dev_err(&pdev->dev, + "failed to get \"ftm_sys\" clock\n"); + return PTR_ERR(fpc->sys_clk); + } + + ret = clk_prepare_enable(fpc->sys_clk); + if (ret) + return ret; + + ftm_writel(fpc->big_endian, 0x00, fpc->base + FTM_CNTIN); + ftm_writel(fpc->big_endian, 0x00, fpc->base + FTM_OUTINIT); + ftm_writel(fpc->big_endian, 0xFF, fpc->base + FTM_OUTMASK); + clk_disable_unprepare(fpc->sys_clk); + + fpc->chip.ops = &fsl_pwm_ops; + fpc->chip.of_xlate = of_pwm_xlate_with_flags; + fpc->chip.of_pwm_n_cells = 3; + fpc->chip.base = -1; + fpc->chip.npwm = 8; + + ret = pwmchip_add(&fpc->chip); + if (ret < 0) { + dev_err(&pdev->dev, "failed to add PWM chip : %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, fpc); + + return 0; +} + +static int fsl_pwm_remove(struct platform_device *pdev) +{ + struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev); + + mutex_destroy(&fpc->lock); + + return pwmchip_remove(&fpc->chip); +} + +static const struct of_device_id fsl_pwm_dt_ids[] = { + { .compatible = "fsl,vf610-ftm-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids); + +static struct platform_driver fsl_pwm_driver = { + .driver = { + .name = "fsl-ftm-pwm", + .of_match_table = fsl_pwm_dt_ids, + }, + .probe = fsl_pwm_probe, + .remove = fsl_pwm_remove, +}; +module_platform_driver(fsl_pwm_driver); + +MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver"); +MODULE_AUTHOR("Xiubo Li "); +MODULE_ALIAS("platform:fsl-ftm-pwm"); +MODULE_LICENSE("GPL");