From patchwork Mon Jan 6 20:55:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 3436721 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 979609F163 for ; Mon, 6 Jan 2014 08:59:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8EC4F20172 for ; Mon, 6 Jan 2014 08:59:23 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C06B2016D for ; Mon, 6 Jan 2014 08:59:22 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W0616-0004wl-HL; Mon, 06 Jan 2014 08:58:36 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W060x-00047R-2C; Mon, 06 Jan 2014 08:58:27 +0000 Received: from va3ehsobe002.messaging.microsoft.com ([216.32.180.12] helo=va3outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W060m-00045T-AA for linux-arm-kernel@lists.infradead.org; Mon, 06 Jan 2014 08:58:17 +0000 Received: from mail37-va3-R.bigfish.com (10.7.14.248) by VA3EHSOBE012.bigfish.com (10.7.40.62) with Microsoft SMTP Server id 14.1.225.22; Mon, 6 Jan 2014 08:57:55 +0000 Received: from mail37-va3 (localhost [127.0.0.1]) by mail37-va3-R.bigfish.com (Postfix) with ESMTP id 047F242013C; Mon, 6 Jan 2014 08:57:55 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6h1082kzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received: from mail37-va3 (localhost.localdomain [127.0.0.1]) by mail37-va3 (MessageSwitch) id 1388998672982230_29026; Mon, 6 Jan 2014 08:57:52 +0000 (UTC) Received: from VA3EHSMHS029.bigfish.com (unknown [10.7.14.227]) by mail37-va3.bigfish.com (Postfix) with ESMTP id E889E2004A; Mon, 6 Jan 2014 08:57:52 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS029.bigfish.com (10.7.99.39) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 6 Jan 2014 08:57:52 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP Server (TLS) id 14.3.158.2; Mon, 6 Jan 2014 08:57:50 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s068vkr6016209; Mon, 6 Jan 2014 01:57:49 -0700 From: Anson Huang To: , Subject: [PATCH 2/3] ARM: imx: add suspend in ocram support on i.mx6dl Date: Mon, 6 Jan 2014 15:55:38 -0500 Message-ID: <1389041739-18389-2-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1389041739-18389-1-git-send-email-b20788@freescale.com> References: <1389041739-18389-1-git-send-email-b20788@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140106_035816_450461_8442DABF X-CRM114-Status: GOOD ( 10.45 ) X-Spam-Score: -0.7 (/) Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP i.MX6DL's suspend in ocram function is derived from i.MX6Q, the only difference is the offset of DDR IO pins, so we need to check cpu type in runtime to set DDR IO to high-Z mode correctly. This patch can lower the DDR IO power from ~26mA@1.5V to ~15mA@1.5V, measured on i.MX6Q/DL SabreSD board, R25. Signed-off-by: Anson Huang --- arch/arm/mach-imx/suspend-imx6.S | 191 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 184 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S index 2ae0354..415dfa0 100644 --- a/arch/arm/mach-imx/suspend-imx6.S +++ b/arch/arm/mach-imx/suspend-imx6.S @@ -24,6 +24,163 @@ .align 3 + .macro imx6dl_ddr_io_save + + ldr r4, [r8, #0x470] /* DRAM_DQM0 */ + ldr r5, [r8, #0x474] /* DRAM_DQM1 */ + ldr r6, [r8, #0x478] /* DRAM_DQM2 */ + ldr r7, [r8, #0x47c] /* DRAM_DQM3 */ + stmfd r10!, {r4-r7} + + ldr r4, [r8, #0x480] /* DRAM_DQM4 */ + ldr r5, [r8, #0x484] /* DRAM_DQM5 */ + ldr r6, [r8, #0x488] /* DRAM_DQM6 */ + ldr r7, [r8, #0x48c] /* DRAM_DQM7 */ + stmfd r10!, {r4-r7} + + ldr r4, [r8, #0x464] /* DRAM_CAS */ + ldr r5, [r8, #0x490] /* DRAM_RAS */ + ldr r6, [r8, #0x4ac] /* DRAM_SDCLK_0 */ + ldr r7, [r8, #0x4b0] /* DRAM_SDCLK_1 */ + stmfd r10!, {r4-r7} + + ldr r5, [r8, #0x750] /* DDRMODE_CTL */ + ldr r6, [r8, #0x760] /* DDRMODE */ + stmfd r10!, {r5-r6} + + ldr r4, [r8, #0x4bc] /* DRAM_SDQS0 */ + ldr r5, [r8, #0x4c0] /* DRAM_SDQS1 */ + ldr r6, [r8, #0x4c4] /* DRAM_SDQS2 */ + ldr r7, [r8, #0x4c8] /* DRAM_SDQS3 */ + stmfd r10!, {r4-r7} + + ldr r4, [r8, #0x4cc] /* DRAM_SDQS4 */ + ldr r5, [r8, #0x4d0] /* DRAM_SDQS5 */ + ldr r6, [r8, #0x4d4] /* DRAM_SDQS6 */ + ldr r7, [r8, #0x4d8] /* DRAM_SDQS7 */ + stmfd r10!, {r4-r7} + + ldr r4, [r8, #0x764] /* GPR_B0DS */ + ldr r5, [r8, #0x770] /* GPR_B1DS */ + ldr r6, [r8, #0x778] /* GPR_B2DS */ + ldr r7, [r8, #0x77c] /* GPR_B3DS */ + stmfd r10!, {r4-r7} + + ldr r4, [r8, #0x780] /* GPR_B4DS */ + ldr r5, [r8, #0x784] /* GPR_B5DS */ + ldr r6, [r8, #0x78c] /* GPR_B6DS */ + ldr r7, [r8, #0x748] /* GPR_B7DS */ + stmfd r10!, {r4-r7} + + ldr r5, [r8, #0x74c] /* GPR_ADDS*/ + ldr r6, [r8, #0x4b4] /* DRAM_SODT0*/ + ldr r7, [r8, #0x4b8] /* DRAM_SODT1*/ + stmfd r10!, {r5-r7} + + .endm + + .macro imx6dl_ddr_io_restore + + ldmea r10!, {r4-r7} + str r4, [r8, #0x470] /* DRAM_DQM0 */ + str r5, [r8, #0x474] /* DRAM_DQM1 */ + str r6, [r8, #0x478] /* DRAM_DQM2 */ + str r7, [r8, #0x47c] /* DRAM_DQM3 */ + + ldmea r10!, {r4-r7} + str r4, [r8, #0x480] /* DRAM_DQM4 */ + str r5, [r8, #0x484] /* DRAM_DQM5 */ + str r6, [r8, #0x488] /* DRAM_DQM6 */ + str r7, [r8, #0x48c] /* DRAM_DQM7 */ + + ldmea r10!, {r4-r7} + str r4, [r8, #0x464] /* DRAM_CAS */ + str r5, [r8, #0x490] /* DRAM_RAS */ + str r6, [r8, #0x4ac] /* DRAM_SDCLK_0 */ + str r7, [r8, #0x4b0] /* DRAM_SDCLK_1 */ + + ldmea r10!, {r5-r6} + str r5, [r8, #0x750] /* DDRMODE_CTL */ + str r6, [r8, #0x760] /* DDRMODE */ + + ldmea r10!, {r4-r7} + str r4, [r8, #0x4bc] /* DRAM_SDQS0 */ + str r5, [r8, #0x4c0] /* DRAM_SDQS1 */ + str r6, [r8, #0x4c4] /* DRAM_SDQS2 */ + str r7, [r8, #0x4c8] /* DRAM_SDQS3 */ + + ldmea r10!, {r4-r7} + str r4, [r8, #0x4cc] /* DRAM_SDQS4 */ + str r5, [r8, #0x4d0] /* DRAM_SDQS5 */ + str r6, [r8, #0x4d4] /* DRAM_SDQS6 */ + str r7, [r8, #0x4d8] /* DRAM_SDQS7 */ + + ldmea r10!, {r4-r7} + str r4, [r8, #0x764] /* GPR_B0DS */ + str r5, [r8, #0x770] /* GPR_B1DS */ + str r6, [r8, #0x778] /* GPR_B2DS */ + str r7, [r8, #0x77c] /* GPR_B3DS */ + + ldmea r10!, {r4-r7} + str r4, [r8, #0x780] /* GPR_B4DS */ + str r5, [r8, #0x784] /* GPR_B5DS */ + str r6, [r8, #0x78c] /* GPR_B6DS */ + str r7, [r8, #0x748] /* GPR_B7DS */ + + ldmea r10!, {r5-r7} + str r5, [r8, #0x74c] /* GPR_ADDS*/ + str r6, [r8, #0x4b4] /* DRAM_SODT0*/ + str r7, [r8, #0x4b8] /* DRAM_SODT1*/ + + .endm + + .macro imx6dl_ddr_io_set_lpm + + mov r10, #0 + str r10, [r8, #0x470] /* DRAM_DQM0 */ + str r10, [r8, #0x474] /* DRAM_DQM1 */ + str r10, [r8, #0x478] /* DRAM_DQM2 */ + str r10, [r8, #0x47c] /* DRAM_DQM3 */ + + str r10, [r8, #0x480] /* DRAM_DQM4 */ + str r10, [r8, #0x484] /* DRAM_DQM5 */ + str r10, [r8, #0x488] /* DRAM_DQM6 */ + str r10, [r8, #0x48c] /* DRAM_DQM7 */ + + str r10, [r8, #0x464] /* DRAM_CAS */ + str r10, [r8, #0x490] /* DRAM_RAS */ + str r10, [r8, #0x4ac] /* DRAM_SDCLK_0 */ + str r10, [r8, #0x4b0] /* DRAM_SDCLK_1 */ + + str r10, [r8, #0x750] /* DDRMODE_CTL */ + str r10, [r8, #0x760] /* DDRMODE */ + + str r10, [r8, #0x4bc] /* DRAM_SDQS0 */ + str r10, [r8, #0x4c0] /* DRAM_SDQS1 */ + str r10, [r8, #0x4c4] /* DRAM_SDQS2 */ + str r10, [r8, #0x4c8] /* DRAM_SDQS3 */ + + str r10, [r8, #0x4cc] /* DRAM_SDQS4 */ + str r10, [r8, #0x4d0] /* DRAM_SDQS5 */ + str r10, [r8, #0x4d4] /* DRAM_SDQS6 */ + str r10, [r8, #0x4d8] /* DRAM_SDQS7 */ + + str r10, [r8, #0x764] /* GPR_B0DS */ + str r10, [r8, #0x770] /* GPR_B1DS */ + str r10, [r8, #0x778] /* GPR_B2DS */ + str r10, [r8, #0x77c] /* GPR_B3DS */ + + str r10, [r8, #0x780] /* GPR_B4DS */ + str r10, [r8, #0x784] /* GPR_B5DS */ + str r10, [r8, #0x78c] /* GPR_B6DS */ + str r10, [r8, #0x748] /* GPR_B7DS */ + + str r10, [r8, #0x74c] /* GPR_ADDS*/ + str r10, [r8, #0x4b4] /* DRAM_SODT0*/ + str r10, [r8, #0x4b8] /* DRAM_SODT1*/ + + .endm + .macro imx6dq_ddr_io_save ldr r4, [r8, #0x5ac] /* DRAM_DQM0 */ @@ -238,9 +395,14 @@ ENTRY(imx6_suspend) ldr r8, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR) - cmp r2, #MXC_CPU_IMX6Q - bne ddr_io_save_dsm_done + cmp r2, #MXC_CPU_IMX6Q + bne dl_io_dsm_save imx6dq_ddr_io_save + b ddr_io_save_dsm_done +dl_io_dsm_save: + cmp r2, #MXC_CPU_IMX6DL + bne ddr_io_save_dsm_done + imx6dl_ddr_io_save ddr_io_save_dsm_done: /* need to sync L2 cache before DSM. */ @@ -267,9 +429,14 @@ poll_dvfs_set_1: ldr r8, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR) - cmp r2, #MXC_CPU_IMX6Q - bne ddr_io_set_lpm_dsm_done + cmp r2, #MXC_CPU_IMX6Q + bne dl_io_dsm_set_lpm imx6dq_ddr_io_set_lpm + b ddr_io_set_lpm_dsm_done +dl_io_dsm_set_lpm: + cmp r2, #MXC_CPU_IMX6DL + bne ddr_io_set_lpm_dsm_done + imx6dl_ddr_io_set_lpm ddr_io_set_lpm_dsm_done: /* @@ -353,9 +520,14 @@ rbc_loop: ldr r8, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR) - cmp r2, #MXC_CPU_IMX6Q - bne ddr_io_restore_done + cmp r2, #MXC_CPU_IMX6Q + bne dl_io_restore imx6dq_ddr_io_restore + b ddr_io_restore_done +dl_io_restore: + cmp r2, #MXC_CPU_IMX6DL + bne ddr_io_restore_done + imx6dl_ddr_io_restore ddr_io_restore_done: ldr r8, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR) @@ -402,8 +574,13 @@ resume: ldr r8, =MX6Q_IOMUXC_BASE_ADDR cmp r2, #MXC_CPU_IMX6Q - bne ddr_io_restore_dsm_done + bne dl_io_dsm_restore imx6dq_ddr_io_restore + b ddr_io_restore_dsm_done +dl_io_dsm_restore: + cmp r2, #MXC_CPU_IMX6DL + bne ddr_io_restore_dsm_done + imx6dl_ddr_io_restore ddr_io_restore_dsm_done: ldr r8, =MX6Q_MMDC_P0_BASE_ADDR