From patchwork Tue Jan 7 11:41:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tushar Behera X-Patchwork-Id: 3447161 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6E63CC02DC for ; Tue, 7 Jan 2014 11:46:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4043120121 for ; Tue, 7 Jan 2014 11:46:12 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B67D92010C for ; Tue, 7 Jan 2014 11:46:10 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W0V6b-0002vY-Gt; Tue, 07 Jan 2014 11:45:57 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W0V6Y-0004EH-U5; Tue, 07 Jan 2014 11:45:54 +0000 Received: from mail-pd0-f172.google.com ([209.85.192.172]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W0V6W-0004Du-0Q for linux-arm-kernel@lists.infradead.org; Tue, 07 Jan 2014 11:45:52 +0000 Received: by mail-pd0-f172.google.com with SMTP id g10so267112pdj.31 for ; Tue, 07 Jan 2014 03:45:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=iNpkh5xihJOvb6SMkH/4uDq0JF50CK/Fxp/PTWpNwew=; b=bwukrTgNDmqJ01y08XgTFv3QeeOXeL0QJUzbEwhOPpd6OQmfFJCSPE/jCNv10nOQob mJZA9K3gG5S0ajecZQXj5vwYNjVg5BAgKWb3eK+yuSHyU1rP2AuTAI9THbvKrPqWyibl CkemciPfOmJN4+FQy+jmqdPQDHUaF8YV2HWNq1P1R9DXyK3cnD4kmjmnUH+6v5VxtZss zohVadeEMq4ND8fK5kKIdsAvlRRuvj8JOU/nGhLHZpDvMBaQUj2/YyEABcsAwhSZyvPT nqhD8Gsv7gjPUORXPt2wDaH4Zvq8lJogM0x8onQka5nwJPIK+aF5lJypwr90c3pruX/N fk0g== X-Gm-Message-State: ALoCoQkW4fzIN7DE+6WGykp3pGzDW2swfW1Lv3tT7A6Z9r8J7xFOZIsnwffQUhg83M2N1cEht0QD X-Received: by 10.68.143.100 with SMTP id sd4mr119088675pbb.0.1389095123991; Tue, 07 Jan 2014 03:45:23 -0800 (PST) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id pa1sm177329749pac.17.2014.01.07.03.45.21 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 07 Jan 2014 03:45:23 -0800 (PST) From: Tushar Behera To: linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH] ARM: cache-l2x0: Parse properties from DT for PL310 cache controller Date: Tue, 7 Jan 2014 17:11:28 +0530 Message-Id: <1389094888-24348-1-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140107_064552_129982_9A43E87E X-CRM114-Status: GOOD ( 11.83 ) X-Spam-Score: -1.9 (-) Cc: linux@arm.linux.org.uk, arnd@arndb.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Parsed auxiliary control properties for PL310 cache controller. Signed-off-by: Tushar Behera --- These properties are set for Exynos4 platform. If we can pass these properties through device tree for Exynos4, then we can remove the hard-coded L2_AUX_VAL. Documentation/devicetree/bindings/arm/l2cc.txt | 10 ++++++++++ arch/arm/include/asm/hardware/cache-l2x0.h | 1 + arch/arm/mm/cache-l2x0.c | 25 ++++++++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index b513cb8..213546d 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -44,6 +44,16 @@ Optional properties: - cache-id-part: cache id part number to be used if it is not present on hardware - wt-override: If present then L2 is forced to Write through mode +- arm,early-write: If present then BRSEP mode (early write response) is enabled. +- arm,data-prefetch: If present then data prefetching is enabled. +- arm,instruction-prefetch: If present then instruction prefetching is enabled. +- arm,ns-interrupt-access: If present then interrupt mask and interrupt clear + registers can be read or modified in both secure or non-secure accesses. +- arm,ns-lockdown: If present then non-secure accesses can write to lockdown + register. +- arm,share-override: If present then shared attribute is ignored internally. +- arm,full-line-of-zero: If present then 'full line of write zero' behaviour is + enabled. Example: diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 6795ff7..aefdec0 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -78,6 +78,7 @@ #define L2X0_CACHE_ID_RTL_R3P2 0x8 #define L2X0_AUX_CTRL_MASK 0xc0000fff +#define L2X0_AUX_CTRL_FULL_LINE_OF_ZERO_SHIFT 0 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3 diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 7abde2c..03357f1 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -705,6 +705,7 @@ static void __init pl310_of_setup(const struct device_node *np, u32 data[3] = { 0, 0, 0 }; u32 tag[3] = { 0, 0, 0 }; u32 filter[2] = { 0, 0 }; + u32 val = 0; of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); if (tag[0] && tag[1] && tag[2]) @@ -731,6 +732,30 @@ static void __init pl310_of_setup(const struct device_node *np, writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN, l2x0_base + L2X0_ADDR_FILTER_START); } + + if (of_find_property(np, "arm,early-write", NULL)) + val |= BIT(L2X0_AUX_CTRL_EARLY_BRESP_SHIFT); + + if (of_find_property(np, "arm,instruction-prefetch", NULL)) + val |= BIT(L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT); + + if (of_find_property(np, "arm,data-prefetch", NULL)) + val |= BIT(L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT); + + if (of_find_property(np, "arm,ns-interrupt-access", NULL)) + val |= BIT(L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT); + + if (of_find_property(np, "arm,ns-lockdown", NULL)) + val |= BIT(L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT); + + if (of_find_property(np, "arm,share-override", NULL)) + val |= BIT(L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT); + + if (of_find_property(np, "arm,full-line-of-zero", NULL)) + val |= BIT(L2X0_AUX_CTRL_FULL_LINE_OF_ZERO_SHIFT); + + *aux_val |= val; + *aux_mask &= ~val; } static void __init pl310_save(void)