From patchwork Mon Jan 13 05:58:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 3473651 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D3CBC9F2E9 for ; Mon, 13 Jan 2014 06:01:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BB6522010E for ; Mon, 13 Jan 2014 06:01:36 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 57B8520107 for ; Mon, 13 Jan 2014 06:01:35 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W2aZE-0004SJ-8R; Mon, 13 Jan 2014 06:00:08 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W2aYv-00057H-5V; Mon, 13 Jan 2014 05:59:49 +0000 Received: from co9ehsobe005.messaging.microsoft.com ([207.46.163.28] helo=co9outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W2aYV-000547-Lm for linux-arm-kernel@lists.infradead.org; Mon, 13 Jan 2014 05:59:25 +0000 Received: from mail149-co9-R.bigfish.com (10.236.132.228) by CO9EHSOBE002.bigfish.com (10.236.130.65) with Microsoft SMTP Server id 14.1.225.22; Mon, 13 Jan 2014 05:59:01 +0000 Received: from mail149-co9 (localhost [127.0.0.1]) by mail149-co9-R.bigfish.com (Postfix) with ESMTP id 619A618013B; Mon, 13 Jan 2014 05:59:01 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6h1082kzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h2438h2461h1155h) Received: from mail149-co9 (localhost.localdomain [127.0.0.1]) by mail149-co9 (MessageSwitch) id 1389592739262139_21172; Mon, 13 Jan 2014 05:58:59 +0000 (UTC) Received: from CO9EHSMHS027.bigfish.com (unknown [10.236.132.245]) by mail149-co9.bigfish.com (Postfix) with ESMTP id 30A7980047; Mon, 13 Jan 2014 05:58:59 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS027.bigfish.com (10.236.130.37) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 13 Jan 2014 05:58:58 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.158.2; Mon, 13 Jan 2014 05:58:58 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s0D5wl69021728; Sun, 12 Jan 2014 22:58:56 -0700 From: Anson Huang To: , Subject: [PATCH V3 5/5] ARM: imx: add suspend in ocram support on i.mx6sl Date: Mon, 13 Jan 2014 13:58:38 +0800 Message-ID: <1389592718-9999-5-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1389592718-9999-1-git-send-email-b20788@freescale.com> References: <1389592718-9999-1-git-send-email-b20788@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140113_005923_940427_C258DB88 X-CRM114-Status: GOOD ( 13.97 ) X-Spam-Score: -4.2 (----) Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP i.MX6SL's suspend in ocram function is derived from i.MX6Q, the only difference is the offset of DDR IO pins. It can lower the DDR IO power from ~10mA@1.2V to ~1mA@1.2V, measured on i.MX6SL EVK board, SH5. Signed-off-by: Anson Huang --- Changes since V2: Do necessary change based on i.mx6q's suspend to ocram function, only cpu type, MMDC IOs' info need changed, and need to add i.mx6sl's special setting/operation during suspend/resume. arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/pm-imx6q.c | 19 ++++++++++ arch/arm/mach-imx/suspend-imx6.S | 74 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 3d96a45..f2df89f 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -105,7 +105,7 @@ ifeq ($(CONFIG_PM),y) AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o suspend-imx6.o # i.MX6SL reuses i.MX6Q code -obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o +obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o suspend-imx6.o endif # i.MX5 based machines diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index 670070b..5350b09 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -67,6 +67,7 @@ #define MX6_MAX_MMDC_IO_NUM 33 #define MX6Q_MMDC_IO_NUM 33 #define MX6DL_MMDC_IO_NUM 33 +#define MX6SL_MMDC_IO_NUM 19 static void __iomem *ccm_base; static void __iomem *suspend_ocram_base; @@ -116,6 +117,14 @@ static u32 imx6dl_mmdc_io_dsm_offset[] = { 0x74c /* GPR_ADDS */ }; +static u32 imx6sl_mmdc_io_dsm_offset[] = { + 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ + 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ + 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */ + 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, DDRMODE_CTL, DDRMODE */ + 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ +}; + /* * This structure is for passing necessary data for low level ocram * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct @@ -448,6 +457,16 @@ static int __init imx6q_ocram_suspend_init(void) readl_relaxed(*(&pm_info->iomuxc_base.vbase) + imx6dl_mmdc_io_dsm_offset[i]); } + } else if (cpu_is_imx6sl()) { + pm_info->cpu_type = MXC_CPU_IMX6SL; + pm_info->mmdc_io_num = MX6SL_MMDC_IO_NUM; + for (i = 0; i < MX6SL_MMDC_IO_NUM; i++) { + pm_info->mmdc_io_val[i][0] = + imx6sl_mmdc_io_dsm_offset[i]; + pm_info->mmdc_io_val[i][1] = + readl_relaxed(*(&pm_info->iomuxc_base.vbase) + + imx6sl_mmdc_io_dsm_offset[i]); + } } imx6_suspend_in_ocram_fn = (void *)fncpy( diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S index da1f806..db4fa8d 100644 --- a/arch/arm/mach-imx/suspend-imx6.S +++ b/arch/arm/mach-imx/suspend-imx6.S @@ -65,6 +65,7 @@ #define MX6Q_SRC_GPR1 0x20 #define MX6Q_SRC_GPR2 0x24 #define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c #define MX6Q_GPC_IMR1 0x08 #define MX6Q_GPC_IMR2 0x0c #define MX6Q_GPC_IMR3 0x10 @@ -143,10 +144,15 @@ poll_dvfs_set_1: ands r7, r7, #(1 << 25) beq poll_dvfs_set_1 + ldr r10, [r0, #PM_INFO_CPU_TYPE_OFFSET] ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET] ldr r6, =0x0 ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET + /* i.MX6SL's last 3 IOs need special setting */ + cmp r10, #MXC_CPU_IMX6SL + bne set_mmdc_io_lpm + sub r7, r7, #0x3 set_mmdc_io_lpm: ldr r9, [r0, r8] str r6, [r11, r9] @@ -155,6 +161,20 @@ set_mmdc_io_lpm: cmp r7, #0x0 bne set_mmdc_io_lpm + cmp r10, #MXC_CPU_IMX6SL + bne set_mmdc_io_lpm_done + ldr r6, =0x1000 + ldr r9, [r0, r8] + str r6, [r11, r9] + add r8, r8, #0x8 + ldr r9, [r0, r8] + str r6, [r11, r9] + add r8, r8, #0x8 + ldr r6, =0x80000 + ldr r9, [r0, r8] + str r6, [r11, r9] +set_mmdc_io_lpm_done: + /* * mask all GPC interrupts before * enabling the RBC counters to @@ -239,6 +259,33 @@ restore_mmdc_io: cmp r6, #0x0 bne restore_mmdc_io + ldr r6, [r0, #PM_INFO_CPU_TYPE_OFFSET] + cmp r6, #MXC_CPU_IMX6SL + bne restore_mmdc_io_done + + ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r11, r7] + orr r6, r6, #(1 << 31) + str r6, [r11, r7] +fifo_reset1_wait: + ldr r6, [r11, r7] + and r6, r6, #(1 << 31) + cmp r6, #0 + bne fifo_reset1_wait + + /* reset FIFO a second time */ + ldr r6, [r11, r7] + orr r6, r6, #(1 << 31) + str r6, [r11, r7] +fifo_reset2_wait: + ldr r6, [r11, r7] + and r6, r6, #(1 << 31) + cmp r6, #0 + bne fifo_reset2_wait +restore_mmdc_io_done: + ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] /* let DDR out of self-refresh. */ ldr r7, [r11, #MX6Q_MMDC_MAPSR] @@ -288,6 +335,33 @@ dsm_restore_mmdc_io: cmp r6, #0x0 bne dsm_restore_mmdc_io + ldr r6, [r0, #PM_INFO_CPU_TYPE_OFFSET] + cmp r6, #MXC_CPU_IMX6SL + bne dsm_restore_mmdc_io_done + + ldr r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r11, r7] + orr r6, r6, #(1 << 31) + str r6, [r11, r7] +dsm_fifo_reset1_wait: + ldr r6, [r11, r7] + and r6, r6, #(1 << 31) + cmp r6, #0 + bne dsm_fifo_reset1_wait + + /* reset FIFO a second time */ + ldr r6, [r11, r7] + orr r6, r6, #(1 << 31) + str r6, [r11, r7] +dsm_fifo_reset2_wait: + ldr r6, [r11, r7] + and r6, r6, #(1 << 31) + cmp r6, #0 + bne dsm_fifo_reset2_wait +dsm_restore_mmdc_io_done: + ldr r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] /* let DDR out of self-refresh */ ldr r7, [r11, #MX6Q_MMDC_MAPSR]