From patchwork Thu Jan 16 08:10:31 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Hesselbarth X-Patchwork-Id: 3497541 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4CB469F2E9 for ; Thu, 16 Jan 2014 08:11:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1E3D620158 for ; Thu, 16 Jan 2014 08:11:55 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E39052010C for ; Thu, 16 Jan 2014 08:11:53 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W3i3B-0002LQ-JS; Thu, 16 Jan 2014 08:11:41 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W3i39-0007QY-D4; Thu, 16 Jan 2014 08:11:39 +0000 Received: from mail-ee0-x235.google.com ([2a00:1450:4013:c00::235]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W3i36-0007P7-1A for linux-arm-kernel@lists.infradead.org; Thu, 16 Jan 2014 08:11:37 +0000 Received: by mail-ee0-f53.google.com with SMTP id t10so1346376eei.12 for ; Thu, 16 Jan 2014 00:11:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U7xUHMNxaZkEVLCrZ7qDRXu0aLryjeUPsK5tltmdZsE=; b=CTVHrMRrkhhJpWKmFaEppSybKwmVhF8uyUhzgAW/56rfqMKv+ASgglUS5K1Puy4Hw7 qlZYx88vcXJDN8CBytQNq4ieVlHPboVyEeSZ0Pxteoh5Qt48RmtjHO/bg8rxMq6kU2pi VevqBHKHbtiFNNGTrny3j/bc8vld674c2o21Xysii7e5FMcPUwEulKRKOLfv8N1DHVuK 550nFGTLQ5jN6aK4esRliyuD0RxNZVE78/XVeupkA6gA51HX2hsxsfAajTDb8P9FScae PM081s15AxPXigiPcNfru+Lf+X5vXuXbc9JJakzPCnlceQBZZFohkEPm6ifz4hjndHl8 Y2Tw== X-Received: by 10.14.208.199 with SMTP id q47mr9914127eeo.77.1389859865922; Thu, 16 Jan 2014 00:11:05 -0800 (PST) Received: from topkick.lan ([82.83.251.183]) by mx.google.com with ESMTPSA id z46sm16393703een.1.2014.01.16.00.11.03 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 16 Jan 2014 00:11:04 -0800 (PST) From: Sebastian Hesselbarth To: Sebastian Hesselbarth Subject: [PATCH] ARM: orion: provide C-style interrupt handler for MULTI_IRQ_HANDLER Date: Thu, 16 Jan 2014 09:10:31 +0100 Message-Id: <1389859831-9883-1-git-send-email-sebastian.hesselbarth@gmail.com> In-Reply-To: <1389775235.10695.51.camel@dagon.hellion.org.uk> References: <1389775235.10695.51.camel@dagon.hellion.org.uk> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140116_031136_197282_5591229E X-CRM114-Status: GOOD ( 18.47 ) X-Spam-Score: -2.0 (--) Cc: Andrew Lunn , Russell King , Jason Cooper , linux-kernel@vger.kernel.org, Ian Campbell , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP DT-enabled Marvell Kirkwood and Dove SoCs make use of an irqchip driver. As expected for irqchip drivers, it uses a C-style interrupt handler and therefore selects MULTI_IRQ_HANDLER. Now, compiling a kernel with both non-DT and DT support enabled, selecting MULTI_IRQ_HANDLER will break ASM irq handler used by non-DT boards. Therefore, we provide a C-style irq handler even for non-DT boards, if MULTI_IRQ_HANDLER is set. By installing the C-style irq handler in orion_irq_init this is transparent to all non-DT board files. While the regression report was filed on Marvell Kirkwood, also Marvell Dove non-DT boards are affected and fixed by this patch. Signed-off-by: Sebastian Hesselbarth Tested-by: Ian Campbell Reported-by: Ian Campbell Fixes: 2326f04321a9 ("ARM: kirkwood: convert to DT irqchip and clocksource") Fixes: f07d73e33d0e ("ARM: dove: convert to DT irqchip and clocksource") Acked-by: Andrew Lunn --- Compared to the two patch version sent on Ian's regression report, I cooked this down to a single patch only touching plat-orion/irq.c. I also dropped Orion5x and MV78x00, as they not yet select MULTI_IRQ_HANDLER at all. Instead I added a comment about taking care of them, as soon as they move over to an irqchip driver themselves. I have not yet Cc'ed this patch to -stable to get some discussion and an Acked-by from Jason or Andrew, too. Cc: Jason Cooper Cc: Andrew Lunn Cc: Sebastian Hesselbarth Cc: Russell King Cc: Ian Campbell Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- arch/arm/plat-orion/irq.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c index c492e1b3dfdb..807df142444b 100644 --- a/arch/arm/plat-orion/irq.c +++ b/arch/arm/plat-orion/irq.c @@ -15,8 +15,51 @@ #include #include #include +#include #include #include +#include + +#ifdef CONFIG_MULTI_IRQ_HANDLER +/* + * Compiling with both non-DT and DT support enabled, will + * break asm irq handler used by non-DT boards. Therefore, + * we provide a C-style irq handler even for non-DT boards, + * if MULTI_IRQ_HANDLER is set. + * + * Notes: + * - this is prepared for Kirkwood and Dove only, update + * accordingly if you add Orion5x or MV78x00. + * - Orion5x uses different macro names and has only one + * set of CAUSE/MASK registers. + * - MV78x00 uses the same macro names but has a third + * set of CAUSE/MASK registers. + * + */ + +static void __iomem *orion_irq_base = IRQ_VIRT_BASE; + +asmlinkage void +__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs) +{ + u32 stat; + + stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF); + stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF); + if (stat) { + unsigned int hwirq = __fls(stat); + handle_IRQ(hwirq, regs); + return; + } + stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF); + stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF); + if (stat) { + unsigned int hwirq = 32 + __fls(stat); + handle_IRQ(hwirq, regs); + return; + } +} +#endif void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) { @@ -35,6 +78,10 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) ct->chip.irq_unmask = irq_gc_mask_set_bit; irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); + +#ifdef CONFIG_MULTI_IRQ_HANDLER + set_handle_irq(orion_legacy_handle_irq); +#endif } #ifdef CONFIG_OF