From patchwork Fri Jan 17 03:39:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 3501781 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B31F39F32F for ; Fri, 17 Jan 2014 03:40:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C8B2C20165 for ; Fri, 17 Jan 2014 03:40:54 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A735820179 for ; Fri, 17 Jan 2014 03:40:53 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W40Hw-0007iD-EF; Fri, 17 Jan 2014 03:40:09 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W40Hn-0006Se-HC; Fri, 17 Jan 2014 03:39:59 +0000 Received: from co9ehsobe004.messaging.microsoft.com ([207.46.163.27] helo=co9outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W40HY-0006RC-Em for linux-arm-kernel@lists.infradead.org; Fri, 17 Jan 2014 03:39:46 +0000 Received: from mail31-co9-R.bigfish.com (10.236.132.253) by CO9EHSOBE016.bigfish.com (10.236.130.79) with Microsoft SMTP Server id 14.1.225.22; Fri, 17 Jan 2014 03:39:22 +0000 Received: from mail31-co9 (localhost [127.0.0.1]) by mail31-co9-R.bigfish.com (Postfix) with ESMTP id A07B32A0299; Fri, 17 Jan 2014 03:39:22 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6h1082kzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h2438h2461h2487h1155h) Received: from mail31-co9 (localhost.localdomain [127.0.0.1]) by mail31-co9 (MessageSwitch) id 1389929958450861_6099; Fri, 17 Jan 2014 03:39:18 +0000 (UTC) Received: from CO9EHSMHS029.bigfish.com (unknown [10.236.132.234]) by mail31-co9.bigfish.com (Postfix) with ESMTP id 7DE801C004E; Fri, 17 Jan 2014 03:39:17 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS029.bigfish.com (10.236.130.39) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 17 Jan 2014 03:39:17 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.3.158.2; Fri, 17 Jan 2014 03:39:16 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s0H3d9VY027931; Thu, 16 Jan 2014 20:39:14 -0700 From: Anson Huang To: , Subject: [PATCH V8 3/3] ARM: imx: add suspend in ocram support for i.mx6sl Date: Fri, 17 Jan 2014 11:39:07 +0800 Message-ID: <1389929947-25707-3-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1389929947-25707-1-git-send-email-b20788@freescale.com> References: <1389929947-25707-1-git-send-email-b20788@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140116_223944_666160_2449E1DA X-CRM114-Status: GOOD ( 13.46 ) X-Spam-Score: -4.2 (----) Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP i.MX6SL's suspend in ocram function is derived from i.MX6Q, it can lower the DDR IO power from ~10mA@1.2V to ~1mA@1.2V, measured on i.MX6SL EVK board, SH5. Signed-off-by: Anson Huang --- Changes since V7: 1. Add __initconst to imx6sl_mmdc_io_offset[]; 2. Add last 3 MMDC IOs lpm settings back, they are missed by mistake in V7. arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/pm-imx6q.c | 20 +++++++++++++++++- arch/arm/mach-imx/suspend-imx6.S | 43 ++++++++++++++++++++++++++++++++++++-- 3 files changed, 61 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 3d96a45..f2df89f 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -105,7 +105,7 @@ ifeq ($(CONFIG_PM),y) AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o suspend-imx6.o # i.MX6SL reuses i.MX6Q code -obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o +obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o suspend-imx6.o endif # i.MX5 based machines diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index c1cbc3b..c8fea8f 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -121,6 +121,14 @@ static const u32 imx6dl_mmdc_io_offset[] __initconst = { 0x74c, /* GPR_ADDS */ }; +static const u32 imx6sl_mmdc_io_offset[] __initconst = { + 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ + 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ + 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */ + 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */ + 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ +}; + static const struct imx6_pm_socdata imx6q_pm_data __initconst = { .cpu_type = MXC_CPU_IMX6Q, .mmdc_compat = "fsl,imx6q-mmdc", @@ -141,6 +149,16 @@ static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { .mmdc_io_offset = imx6dl_mmdc_io_offset, }; +static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { + .cpu_type = MXC_CPU_IMX6SL, + .mmdc_compat = "fsl,imx6sl-mmdc", + .src_compat = "fsl,imx6sl-src", + .iomuxc_compat = "fsl,imx6sl-iomuxc", + .gpc_compat = "fsl,imx6sl-gpc", + .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset), + .mmdc_io_offset = imx6sl_mmdc_io_offset, +}; + /* * This structure is for passing necessary data for low level ocram * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct @@ -532,5 +550,5 @@ void __init imx6dl_pm_init(void) void __init imx6sl_pm_init(void) { - imx6_pm_common_init(NULL); + imx6_pm_common_init(&imx6sl_pm_data); } diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S index d273ee7..81b9d1d 100644 --- a/arch/arm/mach-imx/suspend-imx6.S +++ b/arch/arm/mach-imx/suspend-imx6.S @@ -63,6 +63,7 @@ #define MX6Q_SRC_GPR1 0x20 #define MX6Q_SRC_GPR2 0x24 #define MX6Q_MMDC_MAPSR 0x404 +#define MX6Q_MMDC_MPDGCTRL0 0x83c #define MX6Q_GPC_IMR1 0x08 #define MX6Q_GPC_IMR2 0x0c #define MX6Q_GPC_IMR3 0x10 @@ -107,14 +108,36 @@ ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET] ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET] + cmp r3, #MXC_CPU_IMX6SL + bne 4f + + /* reset read FIFO, RST_RD_FIFO */ + ldr r7, =MX6Q_MMDC_MPDGCTRL0 + ldr r6, [r11, r7] + orr r6, r6, #(1 << 31) + str r6, [r11, r7] +2: + ldr r6, [r11, r7] + ands r6, r6, #(1 << 31) + bne 2b + + /* reset FIFO a second time */ + ldr r6, [r11, r7] + orr r6, r6, #(1 << 31) + str r6, [r11, r7] +3: + ldr r6, [r11, r7] + ands r6, r6, #(1 << 31) + bne 3b +4: /* let DDR out of self-refresh */ ldr r7, [r11, #MX6Q_MMDC_MAPSR] bic r7, r7, #(1 << 21) str r7, [r11, #MX6Q_MMDC_MAPSR] -2: +5: ldr r7, [r11, #MX6Q_MMDC_MAPSR] ands r7, r7, #(1 << 25) - bne 2b + bne 5b /* enable DDR auto power saving */ ldr r7, [r11, #MX6Q_MMDC_MAPSR] @@ -182,12 +205,27 @@ poll_dvfs_set: ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET] ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET add r8, r8, r0 + /* i.MX6SL's last 3 IOs need special setting */ + cmp r3, #MXC_CPU_IMX6SL + subeq r7, r7, #0x3 set_mmdc_io_lpm: ldr r9, [r8], #0x8 str r6, [r11, r9] subs r7, r7, #0x1 bne set_mmdc_io_lpm + cmp r3, #MXC_CPU_IMX6SL + bne set_mmdc_io_lpm_done + ldr r6, =0x1000 + ldr r9, [r8], #0x8 + str r6, [r11, r9] + ldr r9, [r8], #0x8 + str r6, [r11, r9] + ldr r6, =0x80000 + ldr r9, [r8] + str r6, [r11, r9] +set_mmdc_io_lpm_done: + /* * mask all GPC interrupts before * enabling the RBC counters to @@ -282,6 +320,7 @@ resume: str r7, [r11, #MX6Q_SRC_GPR1] str r7, [r11, #MX6Q_SRC_GPR2] + ldr r3, [r0, #PM_INFO_CPU_TYPE_OFFSET] mov r5, #0x1 resume_mmdc