From patchwork Sat Jan 18 12:10:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Abraham X-Patchwork-Id: 3508251 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7494DC02DC for ; Sat, 18 Jan 2014 12:13:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 89F2B20158 for ; Sat, 18 Jan 2014 12:13:40 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6C8A420123 for ; Sat, 18 Jan 2014 12:13:39 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W4Ull-0003W7-Uh; Sat, 18 Jan 2014 12:12:58 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W4Ulc-0003mc-6B; Sat, 18 Jan 2014 12:12:48 +0000 Received: from mail-pa0-x22f.google.com ([2607:f8b0:400e:c03::22f]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W4Ul9-0003ie-SB for linux-arm-kernel@lists.infradead.org; Sat, 18 Jan 2014 12:12:21 +0000 Received: by mail-pa0-f47.google.com with SMTP id kp14so5194465pab.20 for ; Sat, 18 Jan 2014 04:11:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=th1F7cV3D0/yzrowYJJq5xnOYMhcpWPg+FVVCoMtPwI=; b=BcC2yBp6YJ0Yiy9UPjEmKvQly3E+12s9TTX0zV37Ysm2lRlqJu8vHN0PeNfbyNfx1S ceOk1A/hjELAiDhWUqCGbaZbcgb/LPepALI6pxQ+Z7I1/2BkQIgH6W6B8F3lYvf5DfC1 fgxC1kw+N6zjjSk9KbC0AUl7jE6z5Y0nmjZPRrXNdyYqbol0BsThLbttGgJINSYJ6za8 xTDFr8gByGN01SuErqkVdqnspjrz5Iz74n+Vxpum6u5ItFc0yfgh+I0ZMhwnLarzlOsi 6AALvXyxy4nzXtli94msxC86icie3I55ZOo4ZL0F/UiP5BaKwMJtMZADxOanCE1RgItl KYtQ== X-Received: by 10.66.149.7 with SMTP id tw7mr7830891pab.72.1390047117491; Sat, 18 Jan 2014 04:11:57 -0800 (PST) Received: from user-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id gn5sm29858876pbc.29.2014.01.18.04.11.51 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 18 Jan 2014 04:11:56 -0800 (PST) From: Thomas Abraham To: cpufreq@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/7] devicetree: bindings: add cpu clock configuration data binding for Exynos4/5 Date: Sat, 18 Jan 2014 17:40:53 +0530 Message-Id: <1390047057-2239-4-git-send-email-thomas.ab@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1390047057-2239-1-git-send-email-thomas.ab@samsung.com> References: <1390047057-2239-1-git-send-email-thomas.ab@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140118_071220_124582_C61D2D44 X-CRM114-Status: GOOD ( 12.98 ) X-Spam-Score: -2.0 (--) Cc: devicetree@vger.kernel.org, l.majewski@samsung.com, kgene.kim@samsung.com, mturquette@linaro.org, viresh.kumar@linaro.org, t.figa@samsung.com, Rob Herring , linux-samsung-soc@vger.kernel.org, thomas.ab@samsung.com, shawn.guo@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thomas Abraham The clk ops of the new Samsung cpu clock provider type requires configuration data that will be programmed in the multiple clock blocks encapsulated within the cpu clock provider type. This configuration data is held in the clock controller node. Update clock binding documentation about this configuration data format for Samsung Exynos4 and Exynos5 platforms. Cc: Rob Herring Cc: Tomasz Figa Cc: Signed-off-by: Thomas Abraham --- .../devicetree/bindings/clock/exynos4-clock.txt | 30 ++++++++++++++++++++ .../devicetree/bindings/clock/exynos5250-clock.txt | 21 ++++++++++++++ 2 files changed, 51 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index a2ac2d9..c28aabd 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -15,6 +15,29 @@ Required Properties: - #clock-cells: should be 1. +- arm-frequency-table: defines the list of arm clock speeds supported and + the associated configuration values required to setup the clock controller + for generating those speeds. The format of each entry included in the + arm-frequency-table should be as defined below (#cells per entry = 13) + + - for Exynos4210 and Exynos4212 based platforms: + cell #1: arm clock frequency + cell #2: expected arm clock parent frequency + cell #3 ~ cell 12#: value of clock divider in the following order + core_ratio, corem0_ratio, corem1_ratio, periph_ratio, + atb_ratio, pclk_dbg_ratio, apll_ratio, core2_ratio, + copy_ratio, hpm_ratio. + cell #13: reserved (should be zero). + + - for Exynos4412 based platforms: + cell #1: arm clock frequency + cell #2: expected arm clock parent frequency + cell #3 ~ cell #13: value of clock divider in the following order + core_ratio, corem0_ratio, corem1_ratio, periph_ratio, + atb_ratio, pclk_dbg_ratio, apll_ratio, core2_ratio, + copy_ratio, hpm_ratio, cores_ratio + + The following is the list of clocks generated by the controller. Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. Some of the clocks are available only on a particular @@ -275,6 +298,13 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos4210-clock"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + + arm-frequency-table = <1200000 1200000 0 3 7 3 4 1 7 0 5 0>, + <1000000 1000000 0 3 7 3 4 1 7 0 4 0>, + < 800000 800000 0 3 7 3 3 1 7 0 3 0>, + < 500000 500000 0 3 7 3 3 1 7 0 3 0>, + < 400000 400000 0 3 7 3 3 1 7 0 3 0>, + < 200000 200000 0 1 3 1 1 1 0 0 3 0>; }; Example 2: UART controller node that consumes the clock generated by the clock diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 72ce617..99eae9c 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -13,6 +13,20 @@ Required Properties: - #clock-cells: should be 1. +- arm-frequency-table: defines the list of arm clock speeds supported and + the associated configuration values required to setup the clock controller + for generating those speeds. The format of each entry included in the + arm-frequency-table should be as defined below (#cells per entry = 13) + + cell #1: arm clock frequency + cell #2: expected arm clock parent frequency + cell #3 ~ cell #12: value of clock divider in the following order + arm_ratio, cpud_ratio, acp_ratio, periph_ratio, + atb_ratio, pclk_dbg_ratio, apll_ratio, arm2_ratio, + copy_ratio, hpm_ratio + cell #13: reserved (should be zero) + + The following is the list of clocks generated by the controller. Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. @@ -177,6 +191,13 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; + + arm-frequency-table = <1700000 1700000 0 3 7 7 7 3 5 0 0 2>, + <1600000 1600000 0 3 7 7 7 1 4 0 0 2>, + <1500000 1500000 0 2 7 7 7 1 4 0 0 2>, + <1400000 1400000 0 2 7 7 6 1 4 0 0 2>, + <1300000 1300000 0 2 7 7 6 1 3 0 0 2>, + <1200000 1200000 0 2 7 7 5 1 3 0 0 2>; }; Example 2: UART controller node that consumes the clock generated by the clock