From patchwork Sat Jan 18 12:10:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Abraham X-Patchwork-Id: 3508261 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 84FCE9F2E9 for ; Sat, 18 Jan 2014 12:14:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 44C9D20158 for ; Sat, 18 Jan 2014 12:14:02 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B4B8320123 for ; Sat, 18 Jan 2014 12:14:00 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W4Ulw-0003dH-Bx; Sat, 18 Jan 2014 12:13:09 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1W4Ull-0003n6-C5; Sat, 18 Jan 2014 12:12:57 +0000 Received: from mail-pd0-x234.google.com ([2607:f8b0:400e:c02::234]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1W4UlE-0003if-7E for linux-arm-kernel@lists.infradead.org; Sat, 18 Jan 2014 12:12:27 +0000 Received: by mail-pd0-f180.google.com with SMTP id x10so3757389pdj.39 for ; Sat, 18 Jan 2014 04:12:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ccJ9krFtGozOcJV0Z0+5/9dydggmY0TvwJU5DNsfz8c=; b=lCrdWyo7hn0KN2gFz6NkzVLtJ/K2wXhL1vRnmO4QkUONUT4zIygfUt6xz/JEr1DbDb XvBnaoRdmPQtzsGYF7Vjov+TbytyceM3rVnJ24FgWabeAwhJ3wJoN6rwQienLB9S9AO8 0Bmuc7raPbOYkHPq7z4NkATeEqRNNVB65aizmRwVa4V/FpuVTJ6GTeWuz9de2k7mggb0 QRpoPGoxzGjpefqV0CSsc3HyMNmW1y00n+SW5hbTfqr0wk8My6pyjXg3C7Ip8TdCdJsf W//rgRHLumt6eKPXbd00XS2PnfgT6JrRAieXPOkS1q++LB+D9WRU2rpc3eCeuuHCI7tW mmXQ== X-Received: by 10.66.228.37 with SMTP id sf5mr7763228pac.19.1390047122804; Sat, 18 Jan 2014 04:12:02 -0800 (PST) Received: from user-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id gn5sm29858876pbc.29.2014.01.18.04.11.57 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 18 Jan 2014 04:12:01 -0800 (PST) From: Thomas Abraham To: cpufreq@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/7] ARM: dts: Exynos: add cpu nodes, opp and cpu clock frequency table Date: Sat, 18 Jan 2014 17:40:54 +0530 Message-Id: <1390047057-2239-5-git-send-email-thomas.ab@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1390047057-2239-1-git-send-email-thomas.ab@samsung.com> References: <1390047057-2239-1-git-send-email-thomas.ab@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140118_071224_482018_3C567C0A X-CRM114-Status: GOOD ( 11.79 ) X-Spam-Score: -2.0 (--) Cc: l.majewski@samsung.com, kgene.kim@samsung.com, mturquette@linaro.org, viresh.kumar@linaro.org, t.figa@samsung.com, linux-samsung-soc@vger.kernel.org, thomas.ab@samsung.com, shawn.guo@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thomas Abraham For all Exynos based platforms, add CPU nodes, operating points and cpu clock frequency table for migrating from Exynos specific cpufreq driver to using generic cpufreq-cpu0 driver. Signed-off-by: Thomas Abraham --- arch/arm/boot/dts/exynos4210-origen.dts | 6 +++ arch/arm/boot/dts/exynos4210-trats.dts | 6 +++ arch/arm/boot/dts/exynos4210-universal_c210.dts | 6 +++ arch/arm/boot/dts/exynos4210.dtsi | 35 ++++++++++++++++++ arch/arm/boot/dts/exynos4212.dtsi | 17 +++++++++ arch/arm/boot/dts/exynos4412-odroidx.dts | 6 +++ arch/arm/boot/dts/exynos4412-origen.dts | 6 +++ arch/arm/boot/dts/exynos4412-trats2.dts | 6 +++ arch/arm/boot/dts/exynos4412.dtsi | 30 ++++++++++++++++ arch/arm/boot/dts/exynos4x12.dtsi | 35 ++++++++++++++++++ arch/arm/boot/dts/exynos5250-arndale.dts | 6 +++ arch/arm/boot/dts/exynos5250-cros-common.dtsi | 6 +++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 +++ arch/arm/boot/dts/exynos5250.dtsi | 43 ++++++++++++++++++++++- 14 files changed, 213 insertions(+), 1 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 2aa13cb..dd17e93 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -32,6 +32,12 @@ bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; + cpus { + cpu@0 { + cpu0-supply = <&buck1_reg>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 63cc571..25487d7 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -30,6 +30,12 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; }; + cpus { + cpu: cpu@0 { + cpu0-supply = <&varm_breg>; + }; + }; + regulators { compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index d2e3f5f..74d5a70 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -28,6 +28,12 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; }; + cpus { + cpu: cpu@0 { + cpu0-supply = <&vdd_arm_reg>; + }; + }; + mct@10050000 { compatible = "none"; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 48ecd7a..40cd663 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -36,6 +36,34 @@ reg = <0x10023CA0 0x20>; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&clock 12>; + clock-names = "cpu"; + + operating-points = < + 200000 950000 + 400000 975000 + 500000 975000 + 800000 1075000 + 1000000 1150000 + 1200000 1250000 + >; + safe-opp = <800000 1075000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + gic: interrupt-controller@10490000 { cpu-offset = <0x8000>; }; @@ -73,6 +101,13 @@ compatible = "samsung,exynos4210-clock"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + + arm-frequency-table = <1200000 1200000 0 3 7 3 4 1 7 0 5 0 0>, + <1000000 1000000 0 3 7 3 4 1 7 0 4 0 0>, + < 800000 800000 0 3 7 3 3 1 7 0 3 0 0>, + < 500000 500000 0 3 7 3 3 1 7 0 3 0 0>, + < 400000 400000 0 3 7 3 3 1 7 0 3 0 0>, + < 200000 200000 0 1 3 1 1 1 0 0 3 0 0>; }; pmu { diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 94a43f9..2ea0f83 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -22,6 +22,23 @@ / { compatible = "samsung,exynos4212"; + clock: clock-controller@10030000 { + arm-frequency-table = <1500000 1500000 0 3 7 0 6 1 2 0 6 2 0>, + <1400000 1400000 0 3 7 0 6 1 2 0 6 2 0>, + <1300000 1300000 0 3 7 0 5 1 2 0 5 2 0>, + <1200000 1200000 0 3 7 0 5 1 2 0 5 2 0>, + <1100000 1100000 0 3 6 0 4 1 2 0 4 2 0>, + <1000000 1000000 0 2 5 0 4 1 1 0 4 2 0>, + < 900000 900000 0 2 5 0 3 1 1 0 3 2 0>, + < 800000 800000 0 2 5 0 3 1 1 0 3 2 0>, + < 700000 700000 0 2 4 0 3 1 1 0 3 2 0>, + < 600000 600000 0 2 4 0 3 1 1 0 3 2 0>, + < 500000 500000 0 2 4 0 3 1 1 0 3 2 0>, + < 400000 400000 0 2 4 0 3 1 1 0 3 2 0>, + < 300000 300000 0 2 4 0 2 1 1 0 3 2 0>, + < 200000 200000 0 1 3 0 1 1 1 0 3 2 0>; + }; + gic: interrupt-controller@10490000 { cpu-offset = <0x8000>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 12459b0..1c751f9 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -22,6 +22,12 @@ reg = <0x40000000 0x40000000>; }; + cpus { + cpu@0 { + cpu0-supply = <&buck2_reg>; + }; + }; + leds { compatible = "gpio-leds"; led1 { diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 388f035..36080e5 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -27,6 +27,12 @@ bootargs ="console=ttySAC2,115200"; }; + cpus { + cpu@0 { + cpu0-supply = <&buck2_reg>; + }; + }; + firmware@0203F000 { compatible = "samsung,secure-firmware"; reg = <0x0203F000 0x1000>; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 4f851cc..4a4d446 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -31,6 +31,12 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; }; + cpus { + cpu@0 { + cpu0-supply = <&buck2_reg>; + }; + }; + firmware@0204F000 { compatible = "samsung,secure-firmware"; reg = <0x0204F000 0x1000>; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 87b339c..7e9eca7 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -22,6 +22,36 @@ / { compatible = "samsung,exynos4412"; + cpus { + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + }; + }; + + clock: clock-controller@10030000 { + arm-frequency-table = <1500000 1500000 0 3 7 0 6 1 2 0 6 0 7>, + <1400000 1400000 0 3 7 0 6 1 2 0 6 0 6>, + <1300000 1300000 0 3 7 0 5 1 2 0 5 0 6>, + <1200000 1200000 0 3 7 0 5 1 2 0 5 0 5>, + <1100000 1100000 0 3 6 0 4 1 2 0 4 0 5>, + <1000000 1000000 0 2 5 0 4 1 1 0 4 0 4>, + < 900000 900000 0 2 5 0 3 1 1 0 3 0 4>, + < 800000 800000 0 2 5 0 3 1 1 0 3 0 3>, + < 700000 700000 0 2 4 0 3 1 1 0 3 0 3>, + < 600000 600000 0 2 4 0 3 1 1 0 3 0 2>, + < 500000 500000 0 2 4 0 3 1 1 0 3 0 2>, + < 400000 400000 0 2 4 0 3 1 1 0 3 0 1>, + < 300000 300000 0 2 4 0 2 1 1 0 3 0 1>, + < 200000 200000 0 1 3 0 1 1 1 0 3 0 0>; + }; + gic: interrupt-controller@10490000 { cpu-offset = <0x4000>; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 5c412aa..47e2195 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -31,6 +31,41 @@ mshc0 = &mshc_0; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&clock 12>; + clock-names = "cpu"; + + operating-points = < + 1400000 1350000 + 1300000 1287500 + 1200000 1250000 + 1100000 1187500 + 1000000 1137500 + 900000 1087500 + 800000 1037500 + 700000 1000000 + 600000 987500 + 500000 950000 + 400000 925000 + 300000 900000 + 200000 900000 + >; + clock-latency = <200000>; + safe-opp = <800000 1037500>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + pd_isp: isp-power-domain@10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index b42e658..4716eef 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -25,6 +25,12 @@ bootargs = "console=ttySAC2,115200"; }; + cpus { + cpu@0 { + cpu0-supply = <&buck2_reg>; + }; + }; + codec@11000000 { samsung,mfc-r = <0x43000000 0x800000>; samsung,mfc-l = <0x51000000 0x800000>; diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi index 2c1560d..4bde756 100644 --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi @@ -19,6 +19,12 @@ chosen { }; + cpus { + cpu@0 { + cpu0-supply = <&buck2_reg>; + }; + }; + pinctrl@11400000 { /* * Disabled pullups since external part has its own pullups and diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 5c1b7d9..7c228e2 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -27,6 +27,12 @@ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; + cpus { + cpu@0 { + cpu0-supply = <&buck2_reg>; + }; + }; + i2c@12C60000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index b7dec41..d2f98dc 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -61,6 +61,30 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1700000000>; + + clocks = <&clock 12>; + clock-names = "cpu"; + + operating-points = < + 1700000 1300000 + 1600000 1250000 + 1500000 1225000 + 1400000 1200000 + 1300000 1150000 + 1200000 1125000 + 1100000 1100000 + 1000000 1075000 + 900000 1050000 + 800000 1025000 + 700000 1012500 + 600000 1000000 + 500000 975000 + 400000 950000 + 300000 937500 + 200000 925000 + >; + clock-latency = <200000>; + safe-opp = <800000 1025000>; }; cpu@1 { device_type = "cpu"; @@ -84,7 +108,24 @@ compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; - }; + + arm-frequency-table = <1700000 1700000 0 3 7 7 7 3 5 0 0 2 0>, + <1600000 1600000 0 3 7 7 7 1 4 0 0 2 0>, + <1500000 1500000 0 2 7 7 7 1 4 0 0 2 0>, + <1400000 1400000 0 2 7 7 6 1 4 0 0 2 0>, + <1300000 1300000 0 2 7 7 6 1 3 0 0 2 0>, + <1200000 1200000 0 2 7 7 5 1 3 0 0 2 0>, + <1100000 1100000 0 3 7 7 5 1 3 0 0 2 0>, + <1000000 1000000 0 1 7 7 4 1 2 0 0 2 0>, + < 900000 900000 0 1 7 7 4 1 2 0 0 2 0>, + < 800000 800000 0 1 7 7 4 1 2 0 0 2 0>, + < 700000 700000 0 1 7 7 3 1 1 0 0 2 0>, + < 600000 600000 0 1 7 7 3 1 1 0 0 2 0>, + < 500000 500000 0 1 7 7 2 1 1 0 0 2 0>, + < 400000 400000 0 1 7 7 2 1 1 0 0 2 0>, + < 300000 300000 0 1 7 7 1 1 1 0 0 2 0>, + < 200000 200000 0 1 7 7 1 1 1 0 0 2 0>; + }; clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5250-audss-clock";