From patchwork Mon Feb 3 18:33:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liviu Dudau X-Patchwork-Id: 3611591 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 232B39F2D6 for ; Sun, 9 Feb 2014 02:30:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 21A65201BB for ; Sun, 9 Feb 2014 02:30:35 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 07B7220181 for ; Sun, 9 Feb 2014 02:30:34 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WCKA9-0005HV-C8; Sun, 09 Feb 2014 02:30:29 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WCKA6-0005qs-Tx; Sun, 09 Feb 2014 02:30:26 +0000 Received: from fw-tnat.cambridge.arm.com ([217.140.96.21] helo=cam-smtp0.cambridge.arm.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WCKA3-0005oo-IB for linux-arm-kernel@lists.infradead.org; Sun, 09 Feb 2014 02:30:24 +0000 Received: from e106497-lin.cambridge.arm.com (e106497-lin.cambridge.arm.com [10.1.195.173]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id s13IXmZM021308; Mon, 3 Feb 2014 18:33:48 GMT From: Liviu Dudau To: linux-pci , Bjorn Helgaas , Catalin Marinas , Will Deacon Subject: [PATCH] pci: Add support for creating a generic host_bridge from device tree Date: Mon, 3 Feb 2014 18:33:48 +0000 Message-Id: <1391452428-22917-2-git-send-email-Liviu.Dudau@arm.com> X-Mailer: git-send-email 1.8.5.3 In-Reply-To: <1391452428-22917-1-git-send-email-Liviu.Dudau@arm.com> References: <1391452428-22917-1-git-send-email-Liviu.Dudau@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140208_213023_871341_5BD0DD6C X-CRM114-Status: GOOD ( 21.24 ) X-Spam-Score: 0.3 (/) Cc: "devicetree@vger.kernel.org" , linaro-kernel , LKML , LAKML X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00, DATE_IN_PAST_96_XX, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Several platforms use a rather generic version of parsing the device tree to find the host bridge ranges. Move that into the generic PCI code and use it to create a pci_host_bridge structure that can be used by arch code. Based on early attempts by Andrew Murray to unify the code. Used powerpc and microblaze PCI code as starting point. Signed-off-by: Liviu Dudau Cc: Catalin Marinas Cc: Will Deacon --- drivers/pci/host-bridge.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/probe.c | 11 ++++++ include/linux/pci.h | 14 ++++++++ 3 files changed, 117 insertions(+) diff --git a/drivers/pci/host-bridge.c b/drivers/pci/host-bridge.c index 06ace62..9d11deb 100644 --- a/drivers/pci/host-bridge.c +++ b/drivers/pci/host-bridge.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "pci.h" @@ -91,3 +92,94 @@ void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, res->end = region->end + offset; } EXPORT_SYMBOL(pcibios_bus_to_resource); + +/** + * pci_host_bridge_of_get_ranges - Parse PCI host bridge resources from DT + * @dev: device node of the host bridge having the range property + * @resources: list where the range of resources will be added after DT parsing + * + * This function will parse the "ranges" property of a PCI host bridge device + * node and setup the resource mapping based on its content. It is expected + * that the property conforms with the Power ePAPR document. + * + * Each architecture will then apply their filtering based on the limitations + * of each platform. One general restriction seems to be the number of IO space + * ranges, the PCI framework makes intensive use of struct resource management, + * and for IORESOURCE_IO types they can only be requested if they are contained + * within the global ioport_resource, so that should be limited to one IO space + * range. + */ +static int pci_host_bridge_of_get_ranges(struct device_node *dev, + struct list_head *resources) +{ + struct resource *res; + struct of_pci_range range; + struct of_pci_range_parser parser; + int err; + + pr_info("PCI host bridge %s ranges:\n", dev->full_name); + + /* Check for ranges property */ + err = of_pci_range_parser_init(&parser, dev); + if (err) + return err; + + pr_debug("Parsing ranges property...\n"); + for_each_of_pci_range(&parser, &range) { + /* Read next ranges element */ + pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ", + range.pci_space, range.pci_addr); + pr_debug("cpu_addr:0x%016llx size:0x%016llx\n", + range.cpu_addr, range.size); + + /* If we failed translation or got a zero-sized region + * (some FW try to feed us with non sensical zero sized regions + * such as power3 which look like some kind of attempt + * at exposing the VGA memory hole) then skip this range + */ + if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) + continue; + + res = kzalloc(sizeof(struct resource), GFP_KERNEL); + if (!res) { + err = -ENOMEM; + goto bridge_ranges_nomem; + } + + of_pci_range_to_resource(&range, dev, res); + + pci_add_resource_offset(resources, res, + range.cpu_addr - range.pci_addr); + } + + /* Apply architecture specific fixups for the ranges */ + pcibios_fixup_bridge_ranges(resources); + + return 0; + +bridge_ranges_nomem: + pci_free_resource_list(resources); + return err; +} + +struct pci_host_bridge * +pci_host_bridge_of_init(struct device *parent, int busno, struct pci_ops *ops, + void *host_data, struct list_head *resources) +{ + struct pci_bus *root_bus; + struct pci_host_bridge *bridge; + + /* first parse the host bridge bus ranges */ + if (pci_host_bridge_of_get_ranges(parent->of_node, resources)) + return NULL; + + /* then create the root bus */ + root_bus = pci_create_root_bus(parent, busno, ops, host_data, resources); + if (!root_bus) + return NULL; + + bridge = to_pci_host_bridge(root_bus->bridge); + + return bridge; +} +EXPORT_SYMBOL(pci_host_bridge_of_init); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 6e34498..16febae 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1787,6 +1787,17 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus, list_for_each_entry_safe(window, n, resources, list) { list_move_tail(&window->list, &bridge->windows); res = window->res; + /* + * IO resources are stored in the kernel with a CPU start + * address of zero. Adjust the data accordingly and remember + * the offset + */ + if (resource_type(res) == IORESOURCE_IO) { + bridge->io_offset = res->start; + res->end -= res->start; + window->offset -= res->start; + res->start = 0; + } offset = window->offset; if (res->flags & IORESOURCE_BUS) pci_bus_insert_busn_res(b, bus, res->end); diff --git a/include/linux/pci.h b/include/linux/pci.h index fb57c89..8953997 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -394,6 +394,8 @@ struct pci_host_bridge_window { struct pci_host_bridge { struct device dev; struct pci_bus *bus; /* root bus */ + resource_size_t io_offset; /* CPU address offset for io resources */ + int domain_nr; struct list_head windows; /* pci_host_bridge_windows */ void (*release_fn)(struct pci_host_bridge *); void *release_data; @@ -1762,11 +1764,23 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) return bus ? bus->dev.of_node : NULL; } +struct pci_host_bridge * +pci_host_bridge_of_init(struct device *parent, int busno, struct pci_ops *ops, + void *host_data, struct list_head *resources); + +void pcibios_fixup_bridge_ranges(struct list_head *resources); #else /* CONFIG_OF */ static inline void pci_set_of_node(struct pci_dev *dev) { } static inline void pci_release_of_node(struct pci_dev *dev) { } static inline void pci_set_bus_of_node(struct pci_bus *bus) { } static inline void pci_release_bus_of_node(struct pci_bus *bus) { } + +static inline struct pci_host_bridge * +pci_host_bridge_of_init(struct device *parent, struct pci_ops *ops, + void *host_data, struct list_head *resources) +{ + return NULL; +} #endif /* CONFIG_OF */ #ifdef CONFIG_EEH