From patchwork Fri Feb 7 15:55:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Abraham X-Patchwork-Id: 3606331 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 97C639F2E9 for ; Fri, 7 Feb 2014 16:00:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4B7002012B for ; Fri, 7 Feb 2014 16:00:23 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 96CB620163 for ; Fri, 7 Feb 2014 16:00:21 +0000 (UTC) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WBnp1-0000Sf-Ec; Fri, 07 Feb 2014 15:58:33 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WBnoY-0006l1-GS; Fri, 07 Feb 2014 15:58:02 +0000 Received: from mail-pa0-x231.google.com ([2607:f8b0:400e:c03::231]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WBnnx-0006fb-Rk for linux-arm-kernel@lists.infradead.org; Fri, 07 Feb 2014 15:57:29 +0000 Received: by mail-pa0-f49.google.com with SMTP id hz1so3337511pad.36 for ; Fri, 07 Feb 2014 07:57:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=onUSknoSPtna3Q63ACZO+4qSlzBLr80WXDSHqErRCbc=; b=Rr9gAUrdXiE5L2d3Q7/bzHwk5WtPosx6uPanG3ZNhguHX7rfMwO6FpDadx0fNI+VYF 2SrZXuNP3HZzKmmB+mcZg3NBXEhI/jhDi8TEMYLrQtgQ2XkT9hteA2pUbwtYkrU8llQk RkCe5qflxRm+ph2nelNnZovtgsHC6a9JvJf8oIZvnH5MJGI82IMg3AGAVbU8dBMgdYBA gq8l6WlgEC3TvEFY3TCAb5GGqJpBRAlE2btH2ZatMkl6gN2jL+y1ydwrPIb/z03ejNRA /dLkI6GQqE+6QmB6WnoxrjAta5y9mjHzuoEurQNKfpCR+F9yezaVy1C6eTGxoFu0Hrh6 +swg== X-Received: by 10.68.197.8 with SMTP id iq8mr20498382pbc.124.1391788624884; Fri, 07 Feb 2014 07:57:04 -0800 (PST) Received: from user-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id qq5sm14869232pbb.24.2014.02.07.07.56.59 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 07 Feb 2014 07:57:03 -0800 (PST) From: Thomas Abraham To: cpufreq@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 5/7] ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data Date: Fri, 7 Feb 2014 21:25:46 +0530 Message-Id: <1391788548-13056-6-git-send-email-thomas.ab@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1391788548-13056-1-git-send-email-thomas.ab@samsung.com> References: <1391788548-13056-1-git-send-email-thomas.ab@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140207_105726_169610_A10B7A21 X-CRM114-Status: GOOD ( 11.43 ) X-Spam-Score: -2.0 (--) Cc: l.majewski@samsung.com, kgene.kim@samsung.com, mturquette@linaro.org, heiko@sntech.de, viresh.kumar@linaro.org, t.figa@samsung.com, linux-samsung-soc@vger.kernel.org, thomas.ab@samsung.com, shawn.guo@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thomas Abraham For all Exynos based platforms, add CPU nodes, operating points and cpu clock data for migrating from Exynos specific cpufreq driver to using generic cpufreq-cpu0 driver. Signed-off-by: Thomas Abraham --- .../devicetree/bindings/clock/exynos5250-clock.txt | 1 + arch/arm/boot/dts/exynos4210-origen.dts | 6 +++ arch/arm/boot/dts/exynos4210-trats.dts | 6 +++ arch/arm/boot/dts/exynos4210-universal_c210.dts | 6 +++ arch/arm/boot/dts/exynos4210.dtsi | 35 +++++++++++++++++ arch/arm/boot/dts/exynos4212.dtsi | 18 +++++++++ arch/arm/boot/dts/exynos4412-odroidx.dts | 6 +++ arch/arm/boot/dts/exynos4412-origen.dts | 6 +++ arch/arm/boot/dts/exynos4412-trats2.dts | 6 +++ arch/arm/boot/dts/exynos4412.dtsi | 31 +++++++++++++++ arch/arm/boot/dts/exynos4x12.dtsi | 36 +++++++++++++++++ arch/arm/boot/dts/exynos5250-arndale.dts | 6 +++ arch/arm/boot/dts/exynos5250-cros-common.dtsi | 6 +++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 +++ arch/arm/boot/dts/exynos5250.dtsi | 41 ++++++++++++++++++++ 15 files changed, 216 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 9ca818e..4513cbb 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -43,6 +43,7 @@ clock which they consume. ---------------------------- fin_pll 1 + armclk 12 [Clock Gate for Special Clocks] diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 2aa13cb..dd17e93 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -32,6 +32,12 @@ bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; + cpus { + cpu@0 { + cpu0-supply = <&buck1_reg>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 63cc571..25487d76 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -30,6 +30,12 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; }; + cpus { + cpu: cpu@0 { + cpu0-supply = <&varm_breg>; + }; + }; + regulators { compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index d2e3f5f..74d5a70 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -28,6 +28,12 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; }; + cpus { + cpu: cpu@0 { + cpu0-supply = <&vdd_arm_reg>; + }; + }; + mct@10050000 { compatible = "none"; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 48ecd7a..a774247 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -36,6 +36,33 @@ reg = <0x10023CA0 0x20>; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&clock 12>; + clock-names = "cpu"; + + operating-points = < + 1200000 1250000 + 1000000 1150000 + 800000 1075000 + 500000 975000 + 400000 975000 + 200000 950000 + >; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + gic: interrupt-controller@10490000 { cpu-offset = <0x8000>; }; @@ -73,6 +100,14 @@ compatible = "samsung,exynos4210-clock"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1200000 3 7 3 4 1 7 5 0>, + <1000000 3 7 3 4 1 7 4 0>, + < 800000 3 7 3 3 1 7 3 0>, + < 500000 3 7 3 3 1 7 3 0>, + < 400000 3 7 3 3 1 7 3 0>, + < 200000 1 3 1 1 1 0 3 0>; }; pmu { diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 94a43f9..efa8f25 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -22,6 +22,24 @@ / { compatible = "samsung,exynos4212"; + clock: clock-controller@10030000 { + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1500000 3 7 0 6 1 2 6 0>, + <1400000 3 7 0 6 1 2 6 0>, + <1300000 3 7 0 5 1 2 5 0>, + <1200000 3 7 0 5 1 2 5 0>, + <1100000 3 6 0 4 1 2 4 0>, + <1000000 2 5 0 4 1 1 4 0>, + < 900000 2 5 0 3 1 1 3 0>, + < 800000 2 5 0 3 1 1 3 0>, + < 700000 2 4 0 3 1 1 3 0>, + < 600000 2 4 0 3 1 1 3 0>, + < 500000 2 4 0 3 1 1 3 0>, + < 400000 2 4 0 3 1 1 3 0>, + < 300000 2 4 0 2 1 1 3 0>, + < 200000 1 3 0 1 1 1 3 0>; + }; + gic: interrupt-controller@10490000 { cpu-offset = <0x8000>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 9804fcb..04c14dc 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -22,6 +22,12 @@ reg = <0x40000000 0x40000000>; }; + cpus { + cpu@0 { + cpu0-supply = <&buck2_reg>; + }; + }; + leds { compatible = "gpio-leds"; led1 { diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 6bc0539..89bcf2c 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -27,6 +27,12 @@ bootargs ="console=ttySAC2,115200"; }; + cpus { + cpu@0 { + cpu0-supply = <&buck2_reg>; + }; + }; + firmware@0203F000 { compatible = "samsung,secure-firmware"; reg = <0x0203F000 0x1000>; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 4f851cc..4a4d446 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -31,6 +31,12 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; }; + cpus { + cpu@0 { + cpu0-supply = <&buck2_reg>; + }; + }; + firmware@0204F000 { compatible = "samsung,secure-firmware"; reg = <0x0204F000 0x1000>; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 87b339c..f7efdbb 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -22,6 +22,37 @@ / { compatible = "samsung,exynos4412"; + cpus { + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + }; + }; + + clock: clock-controller@10030000 { + samsung,armclk-cells = <10>; + samsung,armclk-divider-table = <1500000 3 7 0 6 1 2 6 0 7>, + <1400000 3 7 0 6 1 2 6 0 6>, + <1300000 3 7 0 5 1 2 5 0 6>, + <1200000 3 7 0 5 1 2 5 0 5>, + <1100000 3 6 0 4 1 2 4 0 5>, + <1000000 2 5 0 4 1 1 4 0 4>, + < 900000 2 5 0 3 1 1 3 0 4>, + < 800000 2 5 0 3 1 1 3 0 3>, + < 700000 2 4 0 3 1 1 3 0 3>, + < 600000 2 4 0 3 1 1 3 0 2>, + < 500000 2 4 0 3 1 1 3 0 2>, + < 400000 2 4 0 3 1 1 3 0 1>, + < 300000 2 4 0 2 1 1 3 0 1>, + < 200000 1 3 0 1 1 1 3 0 0>; + }; + gic: interrupt-controller@10490000 { cpu-offset = <0x4000>; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 5c412aa..c613fc2 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -31,6 +31,42 @@ mshc0 = &mshc_0; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + clocks = <&clock 12>; + clock-names = "cpu"; + + operating-points = < + 1500000 1350000 + 1400000 1287500 + 1300000 1250000 + 1200000 1187500 + 1100000 1137500 + 1000000 1087500 + 900000 1037500 + 800000 1000000 + 700000 987500 + 600000 975000 + 500000 950000 + 400000 925000 + 300000 900000 + 200000 900000 + >; + clock-latency = <200000>; + boost-frequency = <1500000 1350000>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + pd_isp: isp-power-domain@10023CA0 { compatible = "samsung,exynos4210-pd"; reg = <0x10023CA0 0x20>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index b42e658..4716eef 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -25,6 +25,12 @@ bootargs = "console=ttySAC2,115200"; }; + cpus { + cpu@0 { + cpu0-supply = <&buck2_reg>; + }; + }; + codec@11000000 { samsung,mfc-r = <0x43000000 0x800000>; samsung,mfc-l = <0x51000000 0x800000>; diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi index 2c1560d..4bde756 100644 --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi @@ -19,6 +19,12 @@ chosen { }; + cpus { + cpu@0 { + cpu0-supply = <&buck2_reg>; + }; + }; + pinctrl@11400000 { /* * Disabled pullups since external part has its own pullups and diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 3e69837..6ce964f 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -27,6 +27,12 @@ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; + cpus { + cpu@0 { + cpu0-supply = <&buck2_reg>; + }; + }; + i2c@12C60000 { samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <20000>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index b7dec41..0a8545e 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -61,6 +61,29 @@ compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1700000000>; + + clocks = <&clock 12>; + clock-names = "cpu"; + + operating-points = < + 1700000 1300000 + 1600000 1250000 + 1500000 1225000 + 1400000 1200000 + 1300000 1150000 + 1200000 1125000 + 1100000 1100000 + 1000000 1075000 + 900000 1050000 + 800000 1025000 + 700000 1012500 + 600000 1000000 + 500000 975000 + 400000 950000 + 300000 937500 + 200000 925000 + >; + clock-latency = <200000>; }; cpu@1 { device_type = "cpu"; @@ -84,6 +107,24 @@ compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; + + samsung,armclk-cells = <9>; + samsung,armclk-divider-table = <1700000 3 7 7 7 3 5 0 2>, + <1600000 3 7 7 7 1 4 0 2>, + <1500000 2 7 7 7 1 4 0 2>, + <1400000 2 7 7 6 1 4 0 2>, + <1300000 2 7 7 6 1 3 0 2>, + <1200000 2 7 7 5 1 3 0 2>, + <1100000 3 7 7 5 1 3 0 2>, + <1000000 1 7 7 4 1 2 0 2>, + < 900000 1 7 7 4 1 2 0 2>, + < 800000 1 7 7 4 1 2 0 2>, + < 700000 1 7 7 3 1 1 0 2>, + < 600000 1 7 7 3 1 1 0 2>, + < 500000 1 7 7 2 1 1 0 2>, + < 400000 1 7 7 2 1 1 0 2>, + < 300000 1 7 7 1 1 1 0 2>, + < 200000 1 7 7 1 1 1 0 2>; }; clock_audss: audss-clock-controller@3810000 {