From patchwork Mon Feb 10 20:00:02 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 3623031 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 223079F2D6 for ; Mon, 10 Feb 2014 20:07:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1D6AA2013D for ; Mon, 10 Feb 2014 20:07:33 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 09B272010F for ; Mon, 10 Feb 2014 20:07:32 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WCx7H-0002MZ-Az; Mon, 10 Feb 2014 20:06:07 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WCx2N-0004jp-VE; Mon, 10 Feb 2014 20:01:03 +0000 Received: from top.free-electrons.com ([176.31.233.9] helo=mail.free-electrons.com) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WCx27-0004gK-RG for linux-arm-kernel@lists.infradead.org; Mon, 10 Feb 2014 20:00:49 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 48066845; Mon, 10 Feb 2014 21:00:38 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (unknown [190.2.98.212]) by mail.free-electrons.com (Postfix) with ESMTPA id B0BE587B; Mon, 10 Feb 2014 21:00:16 +0100 (CET) From: Ezequiel Garcia To: , Thomas Gleixner Subject: [PATCH 2/2] irqchip: armada-370-xp: Setup a chained handler for the MPIC Date: Mon, 10 Feb 2014 17:00:02 -0300 Message-Id: <1392062402-27357-3-git-send-email-ezequiel.garcia@free-electrons.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1392062402-27357-1-git-send-email-ezequiel.garcia@free-electrons.com> References: <1392062402-27357-1-git-send-email-ezequiel.garcia@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140210_150048_147847_C143D085 X-CRM114-Status: GOOD ( 16.91 ) X-Spam-Score: -1.8 (-) Cc: Thomas Petazzoni , Andrew Lunn , Jason Cooper , Tawfik Bayouk , Lior Amsalem , Ezequiel Garcia , Gregory Clement , Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The new Armada 375 and Armada 38x Marvell SoCs are based on Cortex-A9 CPU cores and use the ARM GIC as their main interrupt controller. However, for various purposes (wake-up from suspend, MSI interrupts), they have kept a separate MPIC interrupt controller, acting as a slave to the GIC. This MPIC was already used as the primary controller on previous Marvell SoCs, so this commit extends the existing driver to allow the MPIC to be used as a GIC slave. Reviewed-by: Gregory CLEMENT Signed-off-by: Ezequiel Garcia --- .../devicetree/bindings/arm/armada-370-xp-mpic.txt | 8 +++- drivers/irqchip/irq-armada-370-xp.c | 50 +++++++++++++++++++--- 2 files changed, 50 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt index d74091a..5fc0313 100644 --- a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt +++ b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt @@ -1,4 +1,4 @@ -Marvell Armada 370 and Armada XP Interrupt Controller +Marvell Armada 370, 375, 38x, XP Interrupt Controller ----------------------------------------------------- Required properties: @@ -16,7 +16,13 @@ Required properties: automatically map to the interrupt controller registers of the current CPU) +Optional properties: +- interrupts: If defined, then it indicates that this MPIC is + connected as a slave to another interrupt controller. This is + typically the case on Armada 375 and Armada 38x, where the MPIC is + connected as a slave to the Cortex-A9 GIC. The provided interrupt + indicate to which GIC interrupt the MPIC output is connected. Example: diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 2ba5761..cd79503 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -42,6 +43,7 @@ #define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4) #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) +#define ARMADA_375_PPI_CAUSE (0x10) #define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4) #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc) @@ -353,7 +355,7 @@ static struct irq_domain_ops armada_370_xp_mpic_irq_ops = { }; #ifdef CONFIG_PCI_MSI -static void armada_370_xp_handle_msi_irq(struct pt_regs *regs) +static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained) { u32 msimask, msinr; @@ -373,13 +375,41 @@ static void armada_370_xp_handle_msi_irq(struct pt_regs *regs) irq = irq_find_mapping(armada_370_xp_msi_domain, msinr - 16); - handle_IRQ(irq, regs); + + if (is_chained) + generic_handle_irq(irq); + else + handle_IRQ(irq, regs); } } #else -static void armada_370_xp_handle_msi_irq(struct pt_regs *r) {} +static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {} #endif +static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq, + struct irq_desc *desc) +{ + struct irq_chip *chip = irq_get_chip(irq); + unsigned long irqmap, irqn; + unsigned int cascade_irq; + + chained_irq_enter(chip, desc); + + irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE); + + if (irqmap & BIT(0)) { + armada_370_xp_handle_msi_irq(NULL, true); + irqmap &= ~BIT(0); + } + + for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) { + cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn); + generic_handle_irq(cascade_irq); + } + + chained_irq_exit(chip, desc); +} + static asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs *regs) { @@ -402,7 +432,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs) /* MSI handling */ if (irqnr == 1) - armada_370_xp_handle_msi_irq(regs); + armada_370_xp_handle_msi_irq(regs, false); #ifdef CONFIG_SMP /* IPI Handling */ @@ -433,6 +463,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node, struct device_node *parent) { struct resource main_int_res, per_cpu_int_res; + int parent_irq; u32 control; BUG_ON(of_address_to_resource(node, 0, &main_int_res)); @@ -461,8 +492,6 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node, BUG_ON(!armada_370_xp_mpic_domain); - irq_set_default_host(armada_370_xp_mpic_domain); - #ifdef CONFIG_SMP armada_xp_mpic_smp_cpu_init(); @@ -478,7 +507,14 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node, armada_370_xp_msi_init(node, main_int_res.start); - set_handle_irq(armada_370_xp_handle_irq); + parent_irq = irq_of_parse_and_map(node, 0); + if (parent_irq <= 0) { + irq_set_default_host(armada_370_xp_mpic_domain); + set_handle_irq(armada_370_xp_handle_irq); + } else { + irq_set_chained_handler(parent_irq, + armada_370_xp_mpic_handle_cascade_irq); + } return 0; }