From patchwork Wed Feb 19 16:58:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 3682501 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 966949F2EC for ; Wed, 19 Feb 2014 17:02:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9EF7A201D5 for ; Wed, 19 Feb 2014 17:02:28 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8DC0F201D3 for ; Wed, 19 Feb 2014 17:02:27 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGAWD-00083Q-3d; Wed, 19 Feb 2014 17:01:09 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGAVr-0000Uc-Vb; Wed, 19 Feb 2014 17:00:47 +0000 Received: from mailout1.samsung.com ([203.254.224.24]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGAVc-0000Rm-1F for linux-arm-kernel@lists.infradead.org; Wed, 19 Feb 2014 17:00:33 +0000 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N1900M4H5WASZ20@mailout1.samsung.com> for linux-arm-kernel@lists.infradead.org; Thu, 20 Feb 2014 02:00:10 +0900 (KST) X-AuditID: cbfee61b-b7f456d000006dfd-34-5304e31af5ef Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 99.CE.28157.A13E4035; Thu, 20 Feb 2014 02:00:10 +0900 (KST) Received: from amdc1344.digital.local ([106.116.147.32]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N19001665U6CW20@mmp2.samsung.com>; Thu, 20 Feb 2014 02:00:10 +0900 (KST) From: Sylwester Nawrocki To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH RFC v1 3/3] clk: Add handling of clk parent and rate assigned from DT Date: Wed, 19 Feb 2014 17:58:44 +0100 Message-id: <1392829124-25705-4-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1392829124-25705-1-git-send-email-s.nawrocki@samsung.com> References: <1392829124-25705-1-git-send-email-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrHLMWRmVeSWpSXmKPExsVy+t9jQV2pxyzBBt97eC3mHznHatH/ZiGr xYE/Oxgtzja9YbfY9Pgaq8Xty7wWa4/cZbdYev0ik8XTCRfZLFr3HmG3OPymndVixuSXbBbr Z7xmceD1WDNvDaNHS3MPm8flvl4mj02rOtk87lzbw+axeUm9R9+WVYwenzfJBXBEcdmkpOZk lqUW6dslcGVsX7SFqWC1ekX/xtlMDYyX5bsYOTgkBEwkDt8U7WLkBDLFJC7cW8/WxcjFISQw nVFi+fLjrBBOB5PEkan32EGq2AQMJXqP9jGC2CICLhKdD9axgBQxC8xjkrjUfpQJJCEsEC5x aOUSZhCbRUBVondTI1gzr4CbxJxrN5kgNitIzJlkAxLmFHCXeHR3BVirEFBJw+lTrBMYeRcw MqxiFE0tSC4oTkrPNdIrTswtLs1L10vOz93ECA7VZ9I7GFc1WBxiFOBgVOLh5bzDEizEmlhW XJl7iFGCg1lJhHfOfaAQb0piZVVqUX58UWlOavEhRmkOFiVx3oOt1oFCAumJJanZqakFqUUw WSYOTqkGxgD+O3ceHFQ2f/jm0EaBvwLWjXn2jW8f+6vO7OBdEGO79f3dtyl9B97Oe+neml7z P25V8+KvH6vmbzhf+PH8gkPHhGpM+P4IPj/6dObxvxNXFR2Z+GS9647rJfM3NGbzNjuo3fH9 8cXKTFH2Z/h9PYvbnnO6tS5K8H6aKG47zyj/Mme+TpXqlB1KLMUZiYZazEXFiQAa7NxRUQIA AA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140219_120032_320696_B77E7AA2 X-CRM114-Status: GOOD ( 14.19 ) X-Spam-Score: -4.6 (----) Cc: mark.rutland@arm.com, linux@arm.linux.org.uk, t.figa@samsung.com, sw0312.kim@samsung.com, kyungmin.park@samsung.com, robh+dt@kernel.org, Sylwester Nawrocki , galak@codeaurora.org, grant.likely@linaro.org, mturquette@linaro.org, m.szyprowski@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This function adds a notifier callback run before a driver is bound to its driver. It will configure parent clock and clock frequencies based on [clk-name]-clk-parent and [clk-name]-clk-rate' DT properties. Signed-off-by: Sylwester Nawrocki Acked-by: Kyungmin Park --- .../devicetree/bindings/clock/clock-bindings.txt | 24 +++++ drivers/clk/clk.c | 92 ++++++++++++++++++++ 2 files changed, 116 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt index 7c52c29..d618498 100644 --- a/Documentation/devicetree/bindings/clock/clock-bindings.txt +++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt @@ -115,3 +115,27 @@ clock signal, and a UART. ("pll" and "pll-switched"). * The UART has its baud clock connected the external oscillator and its register clock connected to the PLL clock (the "pll-switched" signal) + +==Static initial configuration of clock parent and clock frequency== + +Some platforms require static configuration of (parts of) the clock controller +often determined by the board design. Such a configuration can be specified in +a clock consumer node through [clk-name]-clk-parent and [clk-name]-clk-rate DT +properties. The former should contain phandle and clock specifier of the parent +clock, the latter the required clock's frequency value (one cell). "clk-name" +should be listed in the clock-names property and a phandle and a clock specifier +pair corresponding to it should be present in the clocks property. + + uart@a000 { + compatible = "fsl,imx-uart"; + reg = <0xa000 0x1000>; + ... + clocks = <&clkcon 0>, <&clkcon 3>; + clock-names = "baud", "mux"; + + mux-clk-parent = <&pll 1>; + baud-clk-rate = <460800>; + }; + +In this example the pll is set as parent of "mux" clock and frequency of "baud" +clock is specified as 460800 Hz. diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 19f6f3f..9238e08 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include "clk.h" @@ -2527,6 +2528,97 @@ const char *of_clk_get_parent_name(struct device_node *np, int index) } EXPORT_SYMBOL_GPL(of_clk_get_parent_name); +static void __of_clk_assigned_config_set(struct clk *clk, struct clk *pclk, + u32 rate) +{ + int rc; + + if (rate) { + rc = clk_set_rate(clk, rate); + if (rc < 0) + pr_err("clk: couldn't set rate of clock %s (%d)\n", + __clk_get_name(clk), rc); + else + pr_debug("clk: set rate of clock %s to %u\n", + __clk_get_name(clk), rate); + } + + if (!IS_ERR(pclk)) { + rc = clk_set_parent(clk, pclk); + if (rc < 0) + pr_err("clk: couldn't set %s as parent of %s (%d)\n", + __clk_get_name(pclk), __clk_get_name(clk), rc); + else + pr_debug("clk: set %s as parent of %s\n", + __clk_get_name(pclk), __clk_get_name(clk)); + } +} + +static void of_clk_assigned_config_parse(struct device_node *node) +{ + char prop_name[OF_PROP_NAME_MAXLEN]; + struct property *prop; + const char *clk_name; + int rc, index = 0; + + of_property_for_each_string(node, "clock-names", prop, clk_name) { + struct clk *clk, *pclk; + u32 rate = 0; + + snprintf(prop_name, OF_PROP_NAME_MAXLEN, + "%s-clk-parent", clk_name); + pclk = of_clk_get_list_entry(node, prop_name, 0); + + snprintf(prop_name, OF_PROP_NAME_MAXLEN, + "%s-clk-rate", clk_name); + rc = of_property_read_u32(node, prop_name, &rate); + + if (!rc || !IS_ERR(pclk)) { + /* + * Assuming here of_property_for_each_string() returns + * consecutive values of a DT property in ascending + * index order. + */ + clk = of_clk_get(node, index); + + if (!IS_ERR(clk)) + __of_clk_assigned_config_set(clk, pclk, rate); + else + pr_err("clk: couldn't get clk %s\n", clk_name); + } + index++; + } +} + + +static int of_clk_setup_notifier_call(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct device *dev = data; + + if (!dev->of_node) + return NOTIFY_DONE; + + switch (event) { + case BUS_NOTIFY_BIND_DRIVER: + /* Parse and configure DT assigned clock parents and rates */ + of_clk_assigned_config_parse(dev->of_node); + break; + } + + return NOTIFY_DONE; +} + +static struct notifier_block of_clk_setup_nb = { + .notifier_call = of_clk_setup_notifier_call, +}; + +int __init of_clk_setup_notifier_init(void) +{ + return bus_register_notifier(&platform_bus_type, &of_clk_setup_nb); +} +subsys_initcall(of_clk_setup_notifier_init); + /** * of_clk_init() - Scan and init clock providers from the DT * @matches: array of compatible values and init functions for providers.