From patchwork Wed Feb 19 21:11:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 3683101 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 314829F2EC for ; Wed, 19 Feb 2014 21:14:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 51FE1201BA for ; Wed, 19 Feb 2014 21:14:14 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1022720155 for ; Wed, 19 Feb 2014 21:14:13 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGET1-0001oR-UU; Wed, 19 Feb 2014 21:14:08 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGESz-0000DU-GN; Wed, 19 Feb 2014 21:14:05 +0000 Received: from mail-by2on0141.outbound.protection.outlook.com ([207.46.100.141] helo=na01-by2-obe.outbound.protection.outlook.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGESv-0000Cg-WB for linux-arm-kernel@lists.infradead.org; Wed, 19 Feb 2014 21:14:03 +0000 Received: from BL2FFO11FD027.protection.gbl (10.173.160.32) by BL2FFO11HUB015.protection.gbl (10.173.160.107) with Microsoft SMTP Server (TLS) id 15.0.868.13; Wed, 19 Feb 2014 21:13:34 +0000 Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by BL2FFO11FD027.mail.protection.outlook.com (10.173.161.106) with Microsoft SMTP Server (TLS) id 15.0.868.13 via Frontend Transport; Wed, 19 Feb 2014 21:13:33 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.342.0; Wed, 19 Feb 2014 13:00:53 -0800 Received: from linux-builds1.altera.com (linux-builds1.altera.com [137.57.188.114]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id s1JLDRWG004935; Wed, 19 Feb 2014 13:13:31 -0800 (PST) From: To: Subject: [PATCH 3/3] dts: socfpga: Update clock entry to support multiple parents Date: Wed, 19 Feb 2014 15:11:12 -0600 Message-ID: <1392844273-11918-3-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1392844273-11918-1-git-send-email-dinguyen@altera.com> References: <1392844273-11918-1-git-send-email-dinguyen@altera.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:66.35.236.232; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019001)(6009001)(189002)(199002)(87266001)(95666001)(65816001)(87286001)(80022001)(74366001)(69226001)(92726001)(85306002)(93136001)(81542001)(47736001)(74662001)(33646001)(85852003)(80976001)(83072002)(53806001)(81342001)(89996001)(48376002)(86152002)(90146001)(94946001)(56816005)(74502001)(50986001)(4396001)(62966002)(87936001)(46102001)(54316002)(94316002)(49866001)(47976001)(50226001)(95416001)(31966008)(47446002)(20776003)(83322001)(88136002)(74876001)(74706001)(77982001)(81686001)(56776001)(59766001)(50466002)(81816001)(93516002)(86362001)(92566001)(36756003)(47776003)(79102001)(93916002)(77096001)(76786001)(6806004)(19580405001)(19580395003)(76482001)(51856001)(77156001)(44976005)(76796001)(63696002)(53416003); DIR:OUT; SFP:1102; SCL:1; SRVR:BL2FFO11HUB015; H:SJ-ITEXEDGE02.altera.priv.altera.com; CLIP:66.35.236.232; FPR:7F58F45C.C1686CA.91DFA7F8.805A2A9.20204; MLV:nspm; InfoDomainNonexistentMX:1; A:1; LANG:en; X-OriginatorOrg: altera.onmicrosoft.com X-Forefront-PRVS: 012792EC17 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140219_161402_534493_282AD97F X-CRM114-Status: UNSURE ( 9.55 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) Cc: Mike Turquette , Steffen Trumtrar , dinh.linux@gmail.com, Dinh Nguyen X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dinh Nguyen The periph_pll and sdram_pll can have multiple parents. Update the device tree to list all the possible parents for the PLLs. Add an entry for the the f2s_sdram_ref_clk, which is a possible parent for the sdram_pll. Also remove the clock-frequency entry in the f2s_periph_ref_clk, as this property should be placed in dts file. Signed-off-by: Dinh Nguyen Cc: Mike Turquette Cc: Steffen Trumtrar --- arch/arm/boot/dts/socfpga.dtsi | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 7752d7c..6d7eaa4 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -92,7 +92,12 @@ #address-cells = <1>; #size-cells = <0>; - osc: osc1 { + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + osc2: osc2 { #clock-cells = <0>; compatible = "fixed-clock"; }; @@ -100,7 +105,11 @@ f2s_periph_ref_clk: f2s_periph_ref_clk { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <10000000>; + }; + + f2s_sdram_ref_clk: f2s_sdram_ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; }; main_pll: main_pll { @@ -108,7 +117,7 @@ #size-cells = <0>; #clock-cells = <0>; compatible = "altr,socfpga-pll-clock"; - clocks = <&osc>; + clocks = <&osc1>; reg = <0x40>; mpuclk: mpuclk { @@ -162,7 +171,7 @@ #size-cells = <0>; #clock-cells = <0>; compatible = "altr,socfpga-pll-clock"; - clocks = <&osc>; + clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>; reg = <0x80>; emac0_clk: emac0_clk { @@ -213,7 +222,7 @@ #size-cells = <0>; #clock-cells = <0>; compatible = "altr,socfpga-pll-clock"; - clocks = <&osc>; + clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>; reg = <0xC0>; ddr_dqs_clk: ddr_dqs_clk {