From patchwork Thu Feb 20 05:14:41 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Chen X-Patchwork-Id: 3684651 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4DCF49F35F for ; Thu, 20 Feb 2014 06:31:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7AC60201B6 for ; Thu, 20 Feb 2014 06:31:32 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85CA12018A for ; Thu, 20 Feb 2014 06:31:31 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGMrg-0008O7-Lk; Thu, 20 Feb 2014 06:12:09 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGMqo-0002d0-71; Thu, 20 Feb 2014 06:11:14 +0000 Received: from tx2ehsobe004.messaging.microsoft.com ([65.55.88.14] helo=tx2outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WGMpP-0002Rw-C7 for linux-arm-kernel@lists.infradead.org; Thu, 20 Feb 2014 06:09:49 +0000 Received: from mail214-tx2-R.bigfish.com (10.9.14.243) by TX2EHSOBE002.bigfish.com (10.9.40.22) with Microsoft SMTP Server id 14.1.225.22; Thu, 20 Feb 2014 06:09:25 +0000 Received: from mail214-tx2 (localhost [127.0.0.1]) by mail214-tx2-R.bigfish.com (Postfix) with ESMTP id A511FC801AB; Thu, 20 Feb 2014 06:09:25 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah21bch1fc6hzdchz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h2516h2545h255eh1155h) Received: from mail214-tx2 (localhost.localdomain [127.0.0.1]) by mail214-tx2 (MessageSwitch) id 1392876563491409_18059; Thu, 20 Feb 2014 06:09:23 +0000 (UTC) Received: from TX2EHSMHS006.bigfish.com (unknown [10.9.14.234]) by mail214-tx2.bigfish.com (Postfix) with ESMTP id 70594DC0061; Thu, 20 Feb 2014 06:09:23 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS006.bigfish.com (10.9.99.106) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 20 Feb 2014 06:09:20 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP Server (TLS) id 14.3.158.2; Thu, 20 Feb 2014 06:09:20 +0000 Received: from shlinux1.ap.freescale.net (shlinux1.ap.freescale.net [10.192.225.216]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s1K684ee022311; Wed, 19 Feb 2014 23:09:15 -0700 From: Peter Chen To: , , , , , Subject: [PATCH v10 12/15] usb: phy-mxs: Add sync time after controller clear phcd Date: Thu, 20 Feb 2014 13:14:41 +0800 Message-ID: <1392873284-9386-13-git-send-email-peter.chen@freescale.com> X-Mailer: git-send-email 1.7.8 In-Reply-To: <1392873284-9386-1-git-send-email-peter.chen@freescale.com> References: <1392873284-9386-1-git-send-email-peter.chen@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140220_010947_567131_7F4D1905 X-CRM114-Status: UNSURE ( 8.97 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.0 (/) Cc: marex@denx.de, devicetree@vger.kernel.org, m.grzeschik@pengutronix.de, frank.li@freescale.com, linux-doc@vger.kernel.org, alexander.shishkin@linux.intel.com, gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, peter.chen@freescale.com, kernel@pengutronix.de, festevam@gmail.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-0.5 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY, UNRESOLVED_TEMPLATE autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP After clear portsc.phcd, PHY needs 200us stable time for switch 32K clock to AHB clock. Signed-off-by: Peter Chen --- drivers/usb/phy/phy-mxs-usb.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c index 31ef59f..c42bdf0 100644 --- a/drivers/usb/phy/phy-mxs-usb.c +++ b/drivers/usb/phy/phy-mxs-usb.c @@ -151,6 +151,15 @@ static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy) return mxs_phy->data == &imx6sl_phy_data; } +/* + * PHY needs some 32K cycles to switch from 32K clock to + * bus (such as AHB/AXI, etc) clock. + */ +static void mxs_phy_clock_switch_delay(void) +{ + usleep_range(300, 400); +} + static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) { int ret; @@ -261,6 +270,7 @@ static int mxs_phy_init(struct usb_phy *phy) int ret; struct mxs_phy *mxs_phy = to_mxs_phy(phy); + mxs_phy_clock_switch_delay(); ret = clk_prepare_enable(mxs_phy->clk); if (ret) return ret; @@ -289,6 +299,7 @@ static int mxs_phy_suspend(struct usb_phy *x, int suspend) x->io_priv + HW_USBPHY_CTRL_SET); clk_disable_unprepare(mxs_phy->clk); } else { + mxs_phy_clock_switch_delay(); ret = clk_prepare_enable(mxs_phy->clk); if (ret) return ret;