| Message ID | 1393221265-13057-4-git-send-email-lho@apm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sun, Feb 23, 2014 at 10:54:25PM -0700, Loc Ho wrote: > Signed-off-by: Loc Ho <lho@apm.com> > Signed-off-by: Tuan Phan <tphan@apm.com> > Signed-off-by: Suman Tripathi <stripathi@apm.com> This doesn't apply cleanly to libata/for-3.15. How should this be routed? Thanks.
Hi, On Tuesday 25 February 2014 06:44 AM, Loc Ho wrote: > Hi Tejun, > > On Sun, Feb 23, 2014 at 10:54:25PM -0700, Loc Ho wrote: > > Signed-off-by: Loc Ho <lho@apm.com <mailto:lho@apm.com>> > > Signed-off-by: Tuan Phan <tphan@apm.com <mailto:tphan@apm.com>> > > Signed-off-by: Suman Tripathi <stripathi@apm.com <mailto:stripathi@apm.com>> > > This doesn't apply cleanly to libata/for-3.15. How should this be > routed? > > > You need to apply the corresponding PHY driver as well. Are you taken the > corresponding PHY driver into your libata tree? If not, we will need to route > to Kishon generic PHY framework tree. I include Kishon Vijay Abraham to this > email thread. I prefer dt entry go via dt maintainer. However I can add my Acked-by for the dt patches if you can copy me in those patches. > > Kishon, > > Do I need to re-send my SATA PHY driver to you as I had being posting them to > the scsi/arm mailing list? Yes please. Thanks Kishon
Hi Kishon/Tejun, >> > Signed-off-by: Loc Ho <lho@apm.com <mailto:lho@apm.com>> >> > Signed-off-by: Tuan Phan <tphan@apm.com <mailto:tphan@apm.com>> >> > Signed-off-by: Suman Tripathi <stripathi@apm.com <mailto:stripathi@apm.com>> >> >> This doesn't apply cleanly to libata/for-3.15. How should this be >> routed? >> >> >> You need to apply the corresponding PHY driver as well. Are you taken the >> corresponding PHY driver into your libata tree? If not, we will need to route >> to Kishon generic PHY framework tree. I include Kishon Vijay Abraham to this >> email thread. > > I prefer dt entry go via dt maintainer. However I can add my Acked-by for the > dt patches if you can copy me in those patches. The dt email is cc'ed in the patch. Do I need to do anything more here? >> Kishon, >> >> Do I need to re-send my SATA PHY driver to you as I had being posting them to >> the scsi/arm mailing list? > > Yes please. Okay... I will re-post the PHY to you and linux-kernel@vger.kernel.org. -Loc
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi index c78ddcf..57b0770 100644 --- a/arch/arm64/boot/dts/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm-storm.dtsi @@ -221,6 +221,48 @@ enable-offset = <0x0>; enable-mask = <0x06>; }; + + sata01clk: sata01clk@1f21c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "socplldiv2"; + reg = <0x0 0x1f21c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata01clk"; + csr-offset = <0x4>; + csr-mask = <0x05>; + enable-offset = <0x0>; + enable-mask = <0x39>; + }; + + sata23clk: sata23clk@1f22c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "socplldiv2"; + reg = <0x0 0x1f22c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata23clk"; + csr-offset = <0x4>; + csr-mask = <0x05>; + enable-offset = <0x0>; + enable-mask = <0x39>; + }; + + sata45clk: sata45clk@1f23c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "socplldiv2"; + reg = <0x0 0x1f23c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata45clk"; + csr-offset = <0x4>; + csr-mask = <0x05>; + enable-offset = <0x0>; + enable-mask = <0x39>; + }; }; serial0: serial@1c020000 { @@ -262,5 +304,38 @@ apm,tx-boost-gain = <31 31 31 31 31 31>; apm,tx-eye-tuning = <2 10 10 2 10 10>; }; + + sata1: sata@1a000000 { + compatible = "apm,xgene-ahci-sgmii"; + reg = <0x0 0x1a000000 0x0 0x1000>, + <0x0 0x1f210000 0x0 0x10000>; + interrupts = <0x0 0x86 0x4>; + status = "disabled"; + clocks = <&sata01clk 0>; + phys = <&phy1 0>; + phy-names = "sata-6g"; + }; + + sata2: sata@1a400000 { + compatible = "apm,xgene-ahci-sgmii"; + reg = <0x0 0x1a400000 0x0 0x1000>, + <0x0 0x1f220000 0x0 0x10000>; + interrupts = <0x0 0x87 0x4>; + status = "ok"; + clocks = <&sata23clk 0>; + phys = <&phy2 0>; + phy-names = "sata-6g"; + }; + + sata3: sata@1a800000 { + compatible = "apm,xgene-ahci-pcie"; + reg = <0x0 0x1a800000 0x0 0x1000>, + <0x0 0x1f230000 0x0 0x10000>; + interrupts = <0x0 0x88 0x4>; + status = "ok"; + clocks = <&sata45clk 0>; + phys = <&phy3 0>; + phy-names = "sata-6g"; + }; }; };