From patchwork Wed Feb 26 12:50:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 3724011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 67BABBF13A for ; Wed, 26 Feb 2014 12:51:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8C4BA201BA for ; Wed, 26 Feb 2014 12:51:29 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 731782017B for ; Wed, 26 Feb 2014 12:51:28 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WIdxL-0004xd-Jf; Wed, 26 Feb 2014 12:51:23 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WIdxJ-0005VC-3F; Wed, 26 Feb 2014 12:51:21 +0000 Received: from top.free-electrons.com ([176.31.233.9] helo=mail.free-electrons.com) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WIdxF-0005UE-5t for linux-arm-kernel@lists.infradead.org; Wed, 26 Feb 2014 12:51:18 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id A5CDD900; Wed, 26 Feb 2014 13:51:01 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=no version=3.3.1 Received: from localhost.localdomain (unknown [190.2.108.71]) by mail.free-electrons.com (Postfix) with ESMTPA id CB92F7A9; Wed, 26 Feb 2014 13:50:57 +0100 (CET) From: Ezequiel Garcia To: , Jason Gunthorpe , Subject: [PATCH 2/2] ARM: mvebu: system-controller: Add A375 initialization Date: Wed, 26 Feb 2014 09:50:47 -0300 Message-Id: <1393419047-10071-3-git-send-email-ezequiel.garcia@free-electrons.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1393419047-10071-1-git-send-email-ezequiel.garcia@free-electrons.com> References: <1393419047-10071-1-git-send-email-ezequiel.garcia@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140226_075117_458458_8DD6963B X-CRM114-Status: GOOD ( 11.63 ) X-Spam-Score: 1.9 (+) Cc: Thomas Petazzoni , Andrew Lunn , Jason Cooper , Tawfik Bayouk , Wim Van Sebroeck , Lior Amsalem , Ezequiel Garcia , Gregory Clement , Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Level: * X-Virus-Scanned: ClamAV using ClamSMTP The Armada 370/375/XP SoC family watchdog controller has a dedicated RSTOUT register to mask/unmask the watchdog reset. However, the A375 SoC has also a bit to mask the watchdog reset (WDT_RSTOUT), in the RSTOUT global register that is handled by the system-controller. Therefore, let's add a per-SoC initialization routine to unmask the watchdog reset in the shared system-controller register, in this initialization. The dedicated register for watchdog RSTOUT is handled by the watchdog driver, just as is done for the rest of mvebu SoCs. Signed-off-by: Ezequiel Garcia --- arch/arm/mach-mvebu/system-controller.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index 614ba68..96c0a68 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -29,6 +29,8 @@ #include #include "common.h" +#define A375_RSTOUT_WDT_MASK BIT(10) + static void __iomem *system_controller_base; struct mvebu_system_controller { @@ -37,9 +39,33 @@ struct mvebu_system_controller { u32 rstoutn_mask_reset_out_en; u32 system_soft_reset; + + int (*init)(void); }; static struct mvebu_system_controller *mvebu_sc; +int armada_375_system_controller_init(void) +{ + u32 reg; + + /* + * The Armada 370/375/XP SoC family watchdog controller has a + * dedicated RSTOUT register to mask/unmask the watchdog reset. + * However, the A375 SoC also has a bit to mask the watchdog reset + * (WDT_RSTOUT), in the RSTOUT global register that is handled by the + * system-controller. + * + * Therefore, we unmask the watchdog reset in the shared + * system-controller register, in this initialization. The dedicated + * register for watchdog RSTOUT is handled by the watchdog driver. + */ + reg = readl(system_controller_base + mvebu_sc->rstoutn_mask_offset); + reg &= ~A375_RSTOUT_WDT_MASK; + writel(reg, system_controller_base + mvebu_sc->rstoutn_mask_offset); + + return 0; +} + static const struct mvebu_system_controller armada_370_xp_system_controller = { .rstoutn_mask_offset = 0x60, .system_soft_reset_offset = 0x64, @@ -52,6 +78,7 @@ static const struct mvebu_system_controller armada_375_system_controller = { .system_soft_reset_offset = 0x58, .rstoutn_mask_reset_out_en = 0x1, .system_soft_reset = 0x1, + .init = armada_375_system_controller_init, }; static const struct mvebu_system_controller orion_system_controller = { @@ -109,6 +136,9 @@ static int __init mvebu_system_controller_init(void) system_controller_base = of_iomap(np, 0); mvebu_sc = (struct mvebu_system_controller *)match->data; of_node_put(np); + + if (mvebu_sc->init) + mvebu_sc->init(); } return 0;