[PATCHv8,4/7] staging: imx-drm: Use de-active and pixelclk-active display-timings.

Commit Message

Denis Carikli Feb. 26, 2014, 5:51 p.m. UTC

If de-active and/or pixelclk-active properties were set in the
display-timings DT node, they were not used.

Instead the data-enable and the pixel data clock polarity
were hardcoded.

This change is needed for making the eukrea-cpuimx51
  QVGA display work.

Cc: Eric Bénard <[e-mail]>
Cc: Greg Kroah-Hartman <[e-mail]>
Cc: Shawn Guo <[e-mail]>
Cc: [e-mail]
Cc: [e-mail]
Signed-off-by: Denis Carikli <[e-mail]>
---
ChangeLog v7->v8:
- Changed one Cc

ChangeLog v6->v7:
- Shrinked even more the Cc list.
- Rebased the patch
- val is now initialized in imx_pd_connector_get_modes

ChangeLog v5->v6:
- Remove people not concerned by this patch from the Cc list.
- Removed wrong coments from the code.
- Corrected the code style of the "if (!!val)"

ChangeLog v3->v4:
- The old patch was named "staging: imx-drm: ipuv3-crtc: don't harcode some mode".
- Reworked the patch entierly: we now takes the mode flags from the device tree.

ChangeLog v2->v3:
- Added some interested people in the Cc list.
- Ajusted the flags to match the changes in "drm: Add the lacking
  DRM_MODE_FLAG_* for matching the DISPLAY_FLAGS_*"
---
 drivers/staging/imx-drm/imx-drm.h          |    3 +++
 drivers/staging/imx-drm/ipuv3-crtc.c       |    8 ++++++--
 drivers/staging/imx-drm/parallel-display.c |   27 +++++++++++++++++++++++++++
 3 files changed, 36 insertions(+), 2 deletions(-)

Comments

Lothar Waßmann March 6, 2014, 6:58 a.m. UTC | #1

Hi,

Denis Carikli wrote:
> If de-active and/or pixelclk-active properties were set in the
> display-timings DT node, they were not used.
> 
> Instead the data-enable and the pixel data clock polarity
> were hardcoded.
> 
> This change is needed for making the eukrea-cpuimx51
>   QVGA display work.
> 
I just tried this patch on our hardware and found that the pixelclock
polarity is inverse to what the documentation says.

Your patch sets the 'clk_pol' variable in positive logic, while it is
interpreted in negative logic when converted to the final register
value in drivers/staging/imx-drm/ipu-v3/ipu-di.c:

	if (!(sig->clk_pol))
		di_gen |= DI_GEN_POLARITY_DISP_CLK;

IMO this should be
	if (sig->clk_pol)
		di_gen |= DI_GEN_POLARITY_DISP_CLK;

Did you actually measure the resulting clock signal and LCD data?


Lothar Waßmann

Patch

diff --git a/drivers/staging/imx-drm/imx-drm.h b/drivers/staging/imx-drm/imx-drm.h
index aa21028..1893890 100644
--- a/drivers/staging/imx-drm/imx-drm.h
+++ b/drivers/staging/imx-drm/imx-drm.h
@@ -5,6 +5,9 @@ 
 
 #define IPU_PIX_FMT_GBR24	v4l2_fourcc('G', 'B', 'R', '3')
 
+#define IMXDRM_MODE_FLAG_DE_HIGH		(1 << 0)
+#define IMXDRM_MODE_FLAG_PIXDATA_POSEDGE	(1 << 1)
+
 struct device_node;
 struct drm_crtc;
 struct drm_connector;
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index e646017..08c506a 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -157,8 +157,12 @@  static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 		sig_cfg.Vsync_pol = 1;
 
-	sig_cfg.enable_pol = 1;
-	sig_cfg.clk_pol = 1;
+	if (mode->private_flags & IMXDRM_MODE_FLAG_DE_HIGH)
+		sig_cfg.enable_pol = 1;
+
+	if (mode->private_flags & IMXDRM_MODE_FLAG_PIXDATA_POSEDGE)
+		sig_cfg.clk_pol = 1;
+
 	sig_cfg.width = mode->hdisplay;
 	sig_cfg.height = mode->vdisplay;
 	sig_cfg.pixel_fmt = out_pixel_fmt;
diff --git a/drivers/staging/imx-drm/parallel-display.c b/drivers/staging/imx-drm/parallel-display.c
index 12a1b5e..ac55de5 100644
--- a/drivers/staging/imx-drm/parallel-display.c
+++ b/drivers/staging/imx-drm/parallel-display.c
@@ -69,7 +69,34 @@  static int imx_pd_connector_get_modes(struct drm_connector *connector)
 
 	if (np) {
 		struct drm_display_mode *mode = drm_mode_create(connector->dev);
+		struct device_node *timings_np;
+		struct device_node *mode_np;
+		u32 val = 1;
+
 		of_get_drm_display_mode(np, &imxpd->mode, OF_USE_NATIVE_MODE);
+
+		timings_np = of_get_child_by_name(np, "display-timings");
+		if (timings_np) {
+			/* get the display mode node */
+			mode_np = of_parse_phandle(timings_np,
+						   "native-mode", 0);
+			if (!mode_np)
+				mode_np = of_get_next_child(timings_np, NULL);
+
+			/* set de-active to 1 if not set */
+			of_property_read_u32(mode_np, "de-active", &val);
+			if (val) {
+				imxpd->mode.private_flags |=
+					IMXDRM_MODE_FLAG_DE_HIGH;
+			}
+
+			/* set pixelclk-active to 1 if not set */
+			of_property_read_u32(mode_np, "pixelclk-active", &val);
+			if (val) {
+				imxpd->mode.private_flags |=
+					IMXDRM_MODE_FLAG_PIXDATA_POSEDGE;
+			}
+		}
 		drm_mode_copy(mode, &imxpd->mode);
 		mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
 		drm_mode_probed_add(connector, mode);