| Message ID | 1394059489-30706-4-git-send-email-lho@apm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Mar 05, 2014 at 03:44:49PM -0700, Loc Ho wrote:
> This patch adds APM X-Gene SoC AHCI SATA host controller DTS entries.
I pulled the phy branch into libata/for-3.15 but this patch fails to
apply. Can you please regenerate the patches which need to be applied
on top of libata/for-3.15.
Thanks.
Hi Tejun, >> This patch adds APM X-Gene SoC AHCI SATA host controller DTS entries. > > I pulled the phy branch into libata/for-3.15 but this patch fails to > apply. Can you please regenerate the patches which need to be applied > on top of libata/for-3.15. > Kishon didn't applied the PHY DTS patch. Did you first apply the PHY DTS patch? We agreed that you will first pull in the PHY DTS as well as the host controller patches. I don't see any reason why it wouldn't apply if both DTS is applied. I will pull libata/for-3.15 and check out. -Loc
Hello, Loc. On Tue, Mar 11, 2014 at 08:51:37AM -0700, Loc Ho wrote: > Kishon didn't applied the PHY DTS patch. Did you first apply the PHY > DTS patch? We agreed that you will first pull in the PHY DTS as well > as the host controller patches. I don't see any reason why it wouldn't > apply if both DTS is applied. I will pull libata/for-3.15 and check > out. Can you please repost patches to apply on top of the current libata/for-3.15? Thanks.
Hi, >> Kishon didn't applied the PHY DTS patch. Did you first apply the PHY >> DTS patch? We agreed that you will first pull in the PHY DTS as well >> as the host controller patches. I don't see any reason why it wouldn't >> apply if both DTS is applied. I will pull libata/for-3.15 and check >> out. > > Can you please repost patches to apply on top of the current > libata/for-3.15? > I posted v16 yetersday with the PHY DTS merged into the SATA host patches. -Loc
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi index c78ddcf..2a03e96 100644 --- a/arch/arm64/boot/dts/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm-storm.dtsi @@ -221,6 +221,48 @@ enable-offset = <0x0>; enable-mask = <0x06>; }; + + sata01clk: sata01clk@1f21c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "socplldiv2"; + reg = <0x0 0x1f21c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata01clk"; + csr-offset = <0x4>; + csr-mask = <0x05>; + enable-offset = <0x0>; + enable-mask = <0x39>; + }; + + sata23clk: sata23clk@1f22c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "socplldiv2"; + reg = <0x0 0x1f22c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata23clk"; + csr-offset = <0x4>; + csr-mask = <0x05>; + enable-offset = <0x0>; + enable-mask = <0x39>; + }; + + sata45clk: sata45clk@1f23c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "socplldiv2"; + reg = <0x0 0x1f23c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata45clk"; + csr-offset = <0x4>; + csr-mask = <0x05>; + enable-offset = <0x0>; + enable-mask = <0x39>; + }; }; serial0: serial@1c020000 { @@ -262,5 +304,38 @@ apm,tx-boost-gain = <31 31 31 31 31 31>; apm,tx-eye-tuning = <2 10 10 2 10 10>; }; + + sata1: sata@1a000000 { + compatible = "apm,xgene-ahci-sgmii"; + reg = <0x0 0x1a000000 0x0 0x1000>, + <0x0 0x1f210000 0x0 0x10000>; + interrupts = <0x0 0x86 0x4>; + status = "disabled"; + clocks = <&sata01clk 0>; + phys = <&phy1 0>; + phy-names = "sata-phy"; + }; + + sata2: sata@1a400000 { + compatible = "apm,xgene-ahci-sgmii"; + reg = <0x0 0x1a400000 0x0 0x1000>, + <0x0 0x1f220000 0x0 0x10000>; + interrupts = <0x0 0x87 0x4>; + status = "ok"; + clocks = <&sata23clk 0>; + phys = <&phy2 0>; + phy-names = "sata-phy"; + }; + + sata3: sata@1a800000 { + compatible = "apm,xgene-ahci-pcie"; + reg = <0x0 0x1a800000 0x0 0x1000>, + <0x0 0x1f230000 0x0 0x10000>; + interrupts = <0x0 0x88 0x4>; + status = "ok"; + clocks = <&sata45clk 0>; + phys = <&phy3 0>; + phy-names = "sata-phy"; + }; }; };