From patchwork Thu Mar 6 00:24:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 3780551 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4F2239F370 for ; Thu, 6 Mar 2014 00:28:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5EE4B20203 for ; Thu, 6 Mar 2014 00:28:20 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5441B2020E for ; Thu, 6 Mar 2014 00:28:19 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WLM8x-000409-0o; Thu, 06 Mar 2014 00:26:36 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WLM8O-0005vx-3A; Thu, 06 Mar 2014 00:26:00 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WLM7L-0005jb-0A for linux-arm-kernel@lists.infradead.org; Thu, 06 Mar 2014 00:25:03 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s260ON1h000767; Wed, 5 Mar 2014 18:24:23 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s260ONhS010442; Wed, 5 Mar 2014 18:24:23 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Wed, 5 Mar 2014 18:24:22 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s260OMQX016376; Wed, 5 Mar 2014 18:24:22 -0600 Received: from localhost (irmo.am.dhcp.ti.com [128.247.71.175]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s260OMt18373; Wed, 5 Mar 2014 18:24:22 -0600 (CST) From: Suman Anna To: Tony Lindgren , Benoit Cousson Subject: [PATCH 05/10] ARM: OMAP5: hwmod data: add mmu data for ipu & dsp Date: Wed, 5 Mar 2014 18:24:14 -0600 Message-ID: <1394065459-16409-6-git-send-email-s-anna@ti.com> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1394065459-16409-1-git-send-email-s-anna@ti.com> References: <1394065459-16409-1-git-send-email-s-anna@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140305_192455_291039_A60F55B2 X-CRM114-Status: GOOD ( 10.27 ) X-Spam-Score: -6.9 (------) Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Paul Walmsley , Suman Anna , Joerg Roedel , iommu@lists.linux-foundation.org, Laurent Pinchart , linux-omap@vger.kernel.org, Florian Vaussard X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A new MMU hwmod class and data structures are created to represent the MMUs within the IPU and DSP processor subsystems in OMAP5. The MMUs in OMAP5 are identical to those in OMAP4. Cc: Paul Walmsley Cc: Benoit Cousson Signed-off-by: Suman Anna Acked-by: Paul Walmsley --- arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 83 ++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index e297d62..8923172 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -1122,6 +1122,71 @@ static struct omap_hwmod omap54xx_mmc5_hwmod = { }; /* + * 'mmu' class + * The memory management unit performs virtual to physical address translation + * for its requestors. + */ + +static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap54xx_mmu_hwmod_class = { + .name = "mmu", + .sysc = &omap54xx_mmu_sysc, +}; + +static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = { + { .name = "mmu_cache", .rst_shift = 1 }, +}; + +static struct omap_hwmod omap54xx_mmu_dsp_hwmod = { + .name = "mmu_dsp", + .class = &omap54xx_mmu_hwmod_class, + .clkdm_name = "dsp_clkdm", + .rst_lines = omap54xx_mmu_dsp_resets, + .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets), + .main_clk = "dpll_iva_h11x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET, + .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* mmu ipu */ +static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = { + { .name = "mmu_cache", .rst_shift = 2 }, +}; + +static struct omap_hwmod omap54xx_mmu_ipu_hwmod = { + .name = "mmu_ipu", + .class = &omap54xx_mmu_hwmod_class, + .clkdm_name = "ipu_clkdm", + .rst_lines = omap54xx_mmu_ipu_resets, + .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets), + .main_clk = "dpll_core_h22x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET, + .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET, + .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* * 'mpu' class * mpu sub-system */ @@ -1763,6 +1828,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_cfg -> mmu_dsp */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_mmu_dsp_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* mpu -> l3_main_1 */ static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = { .master = &omap54xx_mpu_hwmod, @@ -1787,6 +1860,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main_2 -> mmu_ipu */ +static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = { + .master = &omap54xx_l3_main_2_hwmod, + .slave = &omap54xx_mmu_ipu_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l3_main_1 -> l3_main_3 */ static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = { .master = &omap54xx_l3_main_1_hwmod, @@ -2345,6 +2426,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l4_wkup__counter_32k, &omap54xx_l4_cfg__dma_system, &omap54xx_l4_abe__dmic, + &omap54xx_l4_cfg__mmu_dsp, &omap54xx_mpu__emif1, &omap54xx_mpu__emif2, &omap54xx_l4_wkup__gpio1, @@ -2360,6 +2442,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l4_per__i2c3, &omap54xx_l4_per__i2c4, &omap54xx_l4_per__i2c5, + &omap54xx_l3_main_2__mmu_ipu, &omap54xx_l4_wkup__kbd, &omap54xx_l4_cfg__mailbox, &omap54xx_l4_abe__mcbsp1,