@@ -492,6 +492,16 @@ int imx_drm_encoder_parse_of(struct drm_device *drm,
}
EXPORT_SYMBOL_GPL(imx_drm_encoder_parse_of);
+void imx_drm_set_default_timing_flags(struct drm_display_mode *mode)
+{
+ mode->private_flags &= ~IMXDRM_MODE_FLAG_DE_LOW;
+ mode->private_flags &= ~IMXDRM_MODE_FLAG_PIXDATA_POSEDGE;
+
+ mode->private_flags |= IMXDRM_MODE_FLAG_DE_HIGH;
+ mode->private_flags |= IMXDRM_MODE_FLAG_PIXDATA_NEGEDGE;
+}
+EXPORT_SYMBOL_GPL(imx_drm_set_default_timing_flags);
+
/*
* @node: device tree node containing encoder input ports
* @encoder: drm_encoder
@@ -1,6 +1,11 @@
#ifndef _IMX_DRM_H_
#define _IMX_DRM_H_
+#define IMXDRM_MODE_FLAG_DE_HIGH BIT(0)
+#define IMXDRM_MODE_FLAG_DE_LOW BIT(1)
+#define IMXDRM_MODE_FLAG_PIXDATA_POSEDGE BIT(2)
+#define IMXDRM_MODE_FLAG_PIXDATA_NEGEDGE BIT(3)
+
struct device_node;
struct drm_crtc;
struct drm_connector;
@@ -49,6 +54,7 @@ int imx_drm_encoder_get_mux_id(struct device_node *node,
struct drm_encoder *encoder);
int imx_drm_encoder_parse_of(struct drm_device *drm,
struct drm_encoder *encoder, struct device_node *np);
+void imx_drm_set_default_timing_flags(struct drm_display_mode *mode);
int imx_drm_connector_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode);
@@ -1431,6 +1431,9 @@ static bool imx_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
+ drm_mode_copy(adjusted_mode, mode);
+ imx_drm_set_default_timing_flags(ajusted_mode);
+
return true;
}
@@ -108,6 +108,9 @@ static int imx_ldb_connector_get_modes(struct drm_connector *connector)
mode = drm_mode_create(connector->dev);
if (!mode)
return -EINVAL;
+
+ imx_drm_set_default_timing_flags(&imx_ldb_ch->mode);
+
drm_mode_copy(mode, &imx_ldb_ch->mode);
mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
drm_mode_probed_add(connector, mode);
@@ -294,6 +294,9 @@ static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
+ drm_mode_copy(adjusted_mode, mode);
+ imx_drm_set_default_timing_flags(adjusted_mode);
+
return true;
}
@@ -29,9 +29,11 @@ enum ipuv3_type {
#define CLK_POL_ACTIVE_LOW 0
#define CLK_POL_ACTIVE_HIGH 1
+#define CLK_POL_PRESERVE 2
#define ENABLE_POL_NEGEDGE 0
#define ENABLE_POL_POSEDGE 1
+#define ENABLE_POL_PRESERVE 2
/*
* Bitfield of Display Interface signal polarities.
@@ -43,10 +45,10 @@ struct ipu_di_signal_cfg {
unsigned clksel_en:1;
unsigned clkidle_en:1;
unsigned data_pol:1; /* true = inverted */
- unsigned clk_pol:1;
- unsigned enable_pol:1;
unsigned Hsync_pol:1; /* true = active high */
unsigned Vsync_pol:1;
+ u8 clk_pol;
+ u8 enable_pol;
u16 width;
u16 height;
@@ -597,6 +597,8 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
if (sig->clk_pol == CLK_POL_ACTIVE_HIGH)
di_gen |= DI_GEN_POLARITY_DISP_CLK;
+ else if (sig->clk_pol == CLK_POL_ACTIVE_LOW)
+ di_gen &= ~DI_GEN_POLARITY_DISP_CLK;
ipu_di_write(di, di_gen, DI_GENERAL);
@@ -604,10 +606,13 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
DI_SYNC_AS_GEN);
reg = ipu_di_read(di, DI_POL);
- reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
+ reg &= ~(DI_POL_DRDY_DATA_POLARITY);
if (sig->enable_pol == ENABLE_POL_POSEDGE)
reg |= DI_POL_DRDY_POLARITY_15;
+ else if (sig->enable_pol == ENABLE_POL_NEGEDGE)
+ reg &= ~DI_POL_DRDY_POLARITY_15;
+
if (sig->data_pol)
reg |= DI_POL_DRDY_DATA_POLARITY;
@@ -157,8 +157,16 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
sig_cfg.Vsync_pol = 1;
- sig_cfg.enable_pol = ENABLE_POL_POSEDGE;
- sig_cfg.clk_pol = CLK_POL_ACTIVE_LOW;
+ if (mode->private_flags & IMXDRM_MODE_FLAG_DE_HIGH)
+ sig_cfg.enable_pol = ENABLE_POL_POSEDGE;
+ else if (mode->private_flags & IMXDRM_MODE_FLAG_DE_LOW)
+ sig_cfg.enable_pol = ENABLE_POL_NEGEDGE;
+
+ if (mode->private_flags & IMXDRM_MODE_FLAG_PIXDATA_POSEDGE)
+ sig_cfg.clk_pol = CLK_POL_ACTIVE_HIGH;
+ else if (mode->private_flags & IMXDRM_MODE_FLAG_PIXDATA_NEGEDGE)
+ sig_cfg.clk_pol = CLK_POL_ACTIVE_LOW;
+
sig_cfg.width = mode->hdisplay;
sig_cfg.height = mode->vdisplay;
sig_cfg.pixel_fmt = out_pixel_fmt;
@@ -73,6 +73,7 @@ static int imx_pd_connector_get_modes(struct drm_connector *connector)
if (!mode)
return -EINVAL;
drm_mode_copy(mode, &imxpd->mode);
+ imx_drm_set_default_timing_flags(mode);
mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
drm_mode_probed_add(connector, mode);
num_modes++;
@@ -84,6 +85,7 @@ static int imx_pd_connector_get_modes(struct drm_connector *connector)
return -EINVAL;
of_get_drm_display_mode(np, &imxpd->mode, OF_USE_NATIVE_MODE);
drm_mode_copy(mode, &imxpd->mode);
+ imx_drm_set_default_timing_flags(mode);
mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
drm_mode_probed_add(connector, mode);
num_modes++;
The hardware behaviour was kept. Signed-off-by: Denis Carikli <denis@eukrea.com> --- ChangeLog v9->v10: - New patch that was splitted out of "staging: imx-drm: Use de-active and pixelclk-active display-timings." - The IMXDRM_MODE_FLAG_ are now using the BIT macros. - The SET_CLK_POL and SET_DE_POL masks were removed. The code was updated accordingly. --- drivers/staging/imx-drm/imx-drm-core.c | 10 ++++++++++ drivers/staging/imx-drm/imx-drm.h | 6 ++++++ drivers/staging/imx-drm/imx-hdmi.c | 3 +++ drivers/staging/imx-drm/imx-ldb.c | 3 +++ drivers/staging/imx-drm/imx-tve.c | 3 +++ drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h | 6 ++++-- drivers/staging/imx-drm/ipu-v3/ipu-di.c | 7 ++++++- drivers/staging/imx-drm/ipuv3-crtc.c | 12 ++++++++++-- drivers/staging/imx-drm/parallel-display.c | 2 ++ 9 files changed, 47 insertions(+), 5 deletions(-)