From patchwork Fri Apr 4 23:14:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Soren Brinkmann X-Patchwork-Id: 3941471 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9706EBFF02 for ; Fri, 4 Apr 2014 23:17:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A48F920274 for ; Fri, 4 Apr 2014 23:17:34 +0000 (UTC) Received: from casper.infradead.org (casper.infradead.org [85.118.1.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 45ED220265 for ; Fri, 4 Apr 2014 23:17:33 +0000 (UTC) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WWDKx-0005fh-Tf; Fri, 04 Apr 2014 23:15:53 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WWDKf-0001pu-9s; Fri, 04 Apr 2014 23:15:33 +0000 Received: from mail-qa0-x234.google.com ([2607:f8b0:400d:c00::234]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WWDKJ-0001kl-Fb for linux-arm-kernel@lists.infradead.org; Fri, 04 Apr 2014 23:15:12 +0000 Received: by mail-qa0-f52.google.com with SMTP id m5so3837983qaj.11 for ; Fri, 04 Apr 2014 16:14:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=ulDKK1gyJ6Jj9EtYi6Nqh6pPZGkp/LPqvZk39Bsorbs=; b=bKyoM3ic18NlxWnqw2aA7+uE6W+TgFDthDWmS5DN5Tx3vJrnVg5Xk5Yf3xK3f766e6 EdhXn84Jh7ewz9FSvv1/EtkFVyCn3FTnzr5LvuBSeoqw19Zs0bpCveNNG6mN3wV0s/It 1GI71uTFc57K5qd9TGTrmfn5DiOruZkWKty7Cr87B5BZeotPH5hoYAegGxpfFvOPvdbP vH1r30WId+Pve9bwAK8l8TEqqwh2EDATL1pV5nbMTPpdFMSv8pFdchpbeDWQsUfj1QRy HgxHMfuLvn7TJsWd0I3CG1ZR8oinLsrGykkGnLyBNz74fubpenLRJ4P/vDh5JMH+qWGt Ozjw== X-Received: by 10.140.109.100 with SMTP id k91mr16980768qgf.12.1396653290147; Fri, 04 Apr 2014 16:14:50 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id u7sm18970587qap.5.2014.04.04.16.14.48 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 04 Apr 2014 16:14:49 -0700 (PDT) From: Soren Brinkmann To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Michal Simek Subject: [PATCH v2 4/5] dt-bindings: clock: Add Zynq-7000 header Date: Fri, 4 Apr 2014 16:14:15 -0700 Message-Id: <1396653256-28397-5-git-send-email-soren.brinkmann@xilinx.com> X-Mailer: git-send-email 1.9.1.1.gbb9f595 In-Reply-To: <1396653256-28397-1-git-send-email-soren.brinkmann@xilinx.com> References: <1396653256-28397-1-git-send-email-soren.brinkmann@xilinx.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140404_191511_623603_39A8F1E5 X-CRM114-Status: GOOD ( 12.01 ) X-Spam-Score: -1.9 (-) Cc: devicetree@vger.kernel.org, Mike Looijmans , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Steffen Trumtrar , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add header file with symbolic names for Zynq's clocks. Signed-off-by: Soren Brinkmann --- Changes in v2: - this patch has been added --- include/dt-bindings/clock/zynq-7000.h | 64 +++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 include/dt-bindings/clock/zynq-7000.h diff --git a/include/dt-bindings/clock/zynq-7000.h b/include/dt-bindings/clock/zynq-7000.h new file mode 100644 index 000000000000..851f5cffe481 --- /dev/null +++ b/include/dt-bindings/clock/zynq-7000.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2014 Xilinx Inc. + * Author: Sören Brinkmann + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Zynq 7000 clock controller. +*/ + +#ifndef _DT_BINDINGS_CLOCK_ZYNQ_7000_H +#define _DT_BINDINGS_CLOCK_ZYNQ_7000_H + +#define ZYNQ_CLK_ARMPLL 0 +#define ZYNQ_CLK_DDRPLL 1 +#define ZYNQ_CLK_IOPLL 2 +#define ZYNQ_CLK_CPU_6OR4X 3 +#define ZYNQ_CLK_CPU_3OR2X 4 +#define ZYNQ_CLK_CPU_2X 5 +#define ZYNQ_CLK_CPU_1X 6 +#define ZYNQ_CLK_DDR2X 7 +#define ZYNQ_CLK_DDR3X 8 +#define ZYNQ_CLK_DCI 9 +#define ZYNQ_CLK_LQSPI 10 +#define ZYNQ_CLK_SMC 11 +#define ZYNQ_CLK_PCAP 12 +#define ZYNQ_CLK_GEM0 13 +#define ZYNQ_CLK_GEM1 14 +#define ZYNQ_CLK_FCLK0 15 +#define ZYNQ_CLK_FCLK1 16 +#define ZYNQ_CLK_FCLK2 17 +#define ZYNQ_CLK_FCLK3 18 +#define ZYNQ_CLK_CAN0 19 +#define ZYNQ_CLK_CAN1 20 +#define ZYNQ_CLK_SDIO0 21 +#define ZYNQ_CLK_SDIO1 22 +#define ZYNQ_CLK_UART0 23 +#define ZYNQ_CLK_UART1 24 +#define ZYNQ_CLK_SPI0 25 +#define ZYNQ_CLK_SPI1 26 +#define ZYNQ_CLK_DMA 27 +#define ZYNQ_CLK_USB0_APER 28 +#define ZYNQ_CLK_USB1_APER 29 +#define ZYNQ_CLK_GEM0_APER 30 +#define ZYNQ_CLK_GEM1_APER 31 +#define ZYNQ_CLK_SDIO0_APER 32 +#define ZYNQ_CLK_SDIO1_APER 33 +#define ZYNQ_CLK_SPI0_APER 34 +#define ZYNQ_CLK_SPI1_APER 35 +#define ZYNQ_CLK_CAN0_APER 36 +#define ZYNQ_CLK_CAN1_APER 37 +#define ZYNQ_CLK_I2C0_APER 38 +#define ZYNQ_CLK_I2C1_APER 39 +#define ZYNQ_CLK_UART0_APER 40 +#define ZYNQ_CLK_UART1_APER 41 +#define ZYNQ_CLK_GPIO_APER 42 +#define ZYNQ_CLK_LQSPI_APER 43 +#define ZYNQ_CLK_SMC_APER 44 +#define ZYNQ_CLK_SWDT 45 +#define ZYNQ_CLK_DBG_TRC 46 +#define ZYNQ_CLK_DBG_APB 47 + +#endif /* _DT_BINDINGS_CLOCK_ZYNQ_7000_H */