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[82.83.251.183]) by mx.google.com with ESMTPSA id x45sm50955180eeu.23.2014.04.15.11.16.10 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 15 Apr 2014 11:16:13 -0700 (PDT) From: Sebastian Hesselbarth To: Sebastian Hesselbarth Subject: [PATCH 4/5] ARM: pj4: fix cpu_is_pj4 check Date: Tue, 15 Apr 2014 20:16:02 +0200 Message-Id: <1397585763-23482-5-git-send-email-sebastian.hesselbarth@gmail.com> In-Reply-To: <1397585763-23482-1-git-send-email-sebastian.hesselbarth@gmail.com> References: <20140414151236.75f8816d@skate> <1397585763-23482-1-git-send-email-sebastian.hesselbarth@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140415_111637_256001_17AFC566 X-CRM114-Status: GOOD ( 15.48 ) X-Spam-Score: -0.1 (/) Cc: Thomas Petazzoni , Andrew Lunn , Kevin Hilman , Russell King , Jason Cooper , Arnd Bergmann , Chao Xie , linux-kernel@vger.kernel.org, Haojian Zhuang , Gregory Clement , Olof Johansson , Eric Miao , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit fdb487f5c961b94486a78fa61fa28b8eff1954ab ("ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it has some differences with V7") introduced a cpuid check for Marvell PJ4 processors to fix a regression caused by adding PJ4 based Marvell Dove into multi_v7. Unfortunately, this check is too narrow to catch PJ4 used on Dove itself and breaks iWMMXt support. This patch therefore relaxes the cpuid mask to match both PJ4 and PJ4B. Also, rework the given comment about PJ4/PJ4B modifications to be a little bit more specific about the differences. Signed-off-by: Sebastian Hesselbarth --- Cc: Russell King Cc: Arnd Bergmann Cc: Olof Johansson Cc: Kevin Hilman Cc: Andrew Lunn Cc: Jason Cooper Cc: Gregory Clement Cc: Thomas Petazzoni Cc: Eric Miao Cc: Haojian Zhuang Cc: Chao Xie Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- arch/arm/include/asm/cputype.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index c651e3b26ec7..4764344367d4 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -222,22 +222,22 @@ static inline int cpu_is_xsc3(void) #endif /* - * Marvell's PJ4 core is based on V7 version. It has some modification - * for coprocessor setting. For this reason, we need a way to distinguish - * it. + * Marvell's PJ4 and PJ4B cores are based on V7 version, + * but require a specical sequence for enabling coprocessors. + * For this reason, we need a way to distinguish them. */ -#ifndef CONFIG_CPU_PJ4 -#define cpu_is_pj4() 0 -#else +#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B) static inline int cpu_is_pj4(void) { unsigned int id; id = read_cpuid_id(); - if ((id & 0xfffffff0) == 0x562f5840) + if ((id & 0xff0fff00) == 0x560f5800) return 1; return 0; } +#else +#define cpu_is_pj4() 0 #endif #endif