| Message ID | 1397689719-28882-2-git-send-email-abrestic@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 04/16/2014 05:08 PM, Andrew Bresticker wrote: > Program TEGRA_SDHCI_VENDOR_MISC_CTRL so that UHS modes aren't advertised > in SDHCI_CAPABILITIES_1. While the Tegra SDHCI controller does support > these modes, they require Tegra-specific tuning and calibration routines > which the driver does not support yet. What's the status of patches 1 and 2 in this series? I assumed they'd be applied to the MMC tree. I've had them applied to my local development tree for a while now, so in case this helps: Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> (I thought I wrote that before, but I can't find it, so I must have forgotten to)
Hi Stephen, On Tue, May 20 2014, Stephen Warren wrote: > On 04/16/2014 05:08 PM, Andrew Bresticker wrote: >> Program TEGRA_SDHCI_VENDOR_MISC_CTRL so that UHS modes aren't advertised >> in SDHCI_CAPABILITIES_1. While the Tegra SDHCI controller does support >> these modes, they require Tegra-specific tuning and calibration routines >> which the driver does not support yet. > > What's the status of patches 1 and 2 in this series? I assumed they'd be > applied to the MMC tree. I've had them applied to my local development > tree for a while now, so in case this helps: > > Tested-by: Stephen Warren <swarren@nvidia.com> > Acked-by: Stephen Warren <swarren@nvidia.com> > > (I thought I wrote that before, but I can't find it, so I must have > forgotten to) We've been waiting for a very large sdhci patchset from Russell to land before merging other sdhci patches, but I think we're running out of time for that -- so we'll merge this one way or another within a few days. Thanks, - Chris.
On 21 May 2014 02:43, Chris Ball <chris@printf.net> wrote: > Hi Stephen, > > On Tue, May 20 2014, Stephen Warren wrote: >> On 04/16/2014 05:08 PM, Andrew Bresticker wrote: >>> Program TEGRA_SDHCI_VENDOR_MISC_CTRL so that UHS modes aren't advertised >>> in SDHCI_CAPABILITIES_1. While the Tegra SDHCI controller does support >>> these modes, they require Tegra-specific tuning and calibration routines >>> which the driver does not support yet. >> >> What's the status of patches 1 and 2 in this series? I assumed they'd be >> applied to the MMC tree. I've had them applied to my local development >> tree for a while now, so in case this helps: >> >> Tested-by: Stephen Warren <swarren@nvidia.com> >> Acked-by: Stephen Warren <swarren@nvidia.com> >> >> (I thought I wrote that before, but I can't find it, so I must have >> forgotten to) > > We've been waiting for a very large sdhci patchset from Russell to > land before merging other sdhci patches, but I think we're running > out of time for that -- so we'll merge this one way or another within > a few days. > > Thanks, > > - Chris. > -- > Chris Ball <http://printf.net/> Hi Stephen/Andrew, I tried to include the v2 of patch1 and patch2 in PR I just sent to Chris - but needed to omit them due to conflicts. Could you please re-base them on top of my PR and resend them? I suppose Chris can take them separately once he pulled my PR. Kind regards Ulf Hansson
> Hi Stephen/Andrew, > > I tried to include the v2 of patch1 and patch2 in PR I just sent to > Chris - but needed to omit them due to conflicts. > > Could you please re-base them on top of my PR and resend them? I > suppose Chris can take them separately once he pulled my PR. Will do. Thanks, Andrew
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index a835898..3cadd9c 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -32,11 +32,17 @@ /* Tegra SDHOST controller vendor register definitions */ #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120 +#define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8 +#define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 +#define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) +#define NVQUIRK_DISABLE_SDR50 BIT(3) +#define NVQUIRK_DISABLE_SDR104 BIT(4) +#define NVQUIRK_DISABLE_DDR50 BIT(5) struct sdhci_tegra_soc_data { const struct sdhci_pltfm_data *pdata; @@ -113,18 +119,23 @@ static void tegra_sdhci_reset_exit(struct sdhci_host *host, u8 mask) struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = pltfm_host->priv; const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; + u32 misc_ctrl; if (!(mask & SDHCI_RESET_ALL)) return; + misc_ctrl = sdhci_readw(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); /* Erratum: Enable SDHCI spec v3.00 support */ - if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) { - u32 misc_ctrl; - - misc_ctrl = sdhci_readb(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); + if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300; - sdhci_writeb(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); - } + /* Don't advertise UHS modes which aren't supported yet */ + if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR50) + misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR50; + if (soc_data->nvquirks & NVQUIRK_DISABLE_DDR50) + misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_DDR50; + if (soc_data->nvquirks & NVQUIRK_DISABLE_SDR104) + misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_SDR104; + sdhci_writew(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); } static int tegra_sdhci_buswidth(struct sdhci_host *host, int bus_width) @@ -181,7 +192,9 @@ static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { static struct sdhci_tegra_soc_data soc_data_tegra30 = { .pdata = &sdhci_tegra30_pdata, - .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300, + .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 | + NVQUIRK_DISABLE_SDR50 | + NVQUIRK_DISABLE_SDR104, }; static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { @@ -195,6 +208,9 @@ static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { static struct sdhci_tegra_soc_data soc_data_tegra114 = { .pdata = &sdhci_tegra114_pdata, + .nvquirks = NVQUIRK_DISABLE_SDR50 | + NVQUIRK_DISABLE_DDR50 | + NVQUIRK_DISABLE_SDR104, }; static const struct of_device_id sdhci_tegra_dt_match[] = {
Program TEGRA_SDHCI_VENDOR_MISC_CTRL so that UHS modes aren't advertised in SDHCI_CAPABILITIES_1. While the Tegra SDHCI controller does support these modes, they require Tegra-specific tuning and calibration routines which the driver does not support yet. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> --- No changes from v1 --- drivers/mmc/host/sdhci-tegra.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-)