From patchwork Wed Apr 16 23:08:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 4004431 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 01EE5C0DA2 for ; Wed, 16 Apr 2014 23:11:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 93BF4201C7 for ; Wed, 16 Apr 2014 23:11:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C58FA2017B for ; Wed, 16 Apr 2014 23:11:45 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WaYxN-0004FV-18; Wed, 16 Apr 2014 23:09:29 +0000 Received: from mail-qa0-f73.google.com ([209.85.216.73]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WaYxF-0002XA-Ef for linux-arm-kernel@lists.infradead.org; Wed, 16 Apr 2014 23:09:21 +0000 Received: by mail-qa0-f73.google.com with SMTP id hw13so1712130qab.0 for ; Wed, 16 Apr 2014 16:09:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZwyGwR8ebVWkEn6bmfF/ar4yeaF/DO2a+DOZxSVTVog=; b=L/DUAy0FomIg31jPB7VVutziPBnxv/Ch6hJiRReMioYRKhevr0u40kSPzft/2xK6B9 EjyAIOCL3y/rHXLndcIYs/BNnCdCRZjbp1dLJP+QTmvDQDKIq846eV6W8iK/+a1sT0Oc +Xrl5mk/kgGNZKCVXN2Hg1jtvsVvyhMB3nUN1leOGcYWJ75WRHipuMyNlB+tEM/6XL0q gTvjpocYsRsz6sEOqXUnL6vZ6/sCbeplTFv1ow36uE4vK6sTTHPUoRMvvkpR72pPGNeT 2XnJMA1eNenpAteUdjP/ZhiFGUBIzOWO8OFUHveK5u3mxwsZbF945YTlLEVD6Hv3LM6d qmng== X-Gm-Message-State: ALoCoQlIcnSd+HhTuNDmKfrID5yqb+iSW0C7SJn6ztMWdNkXVXngwcx+ia5/GmZh0MKjbyvCby0wsgfIA6975a2Zb3DmoOMvaGrf8vf+b7JduCxOmM0z0CmQv7VJ3N1J5NYS92BdSMJpAh0jAYDPhRhNEi7yirIYvm+9eCss2/+d4qNTtjYAhR4JjxCJjiVjMwc7qKzZAP2+eemckTtLwsfCYVIRVN9wDA== X-Received: by 10.58.111.202 with SMTP id ik10mr5220187veb.4.1397689740055; Wed, 16 Apr 2014 16:09:00 -0700 (PDT) Received: from corp2gmr1-2.hot.corp.google.com (corp2gmr1-2.hot.corp.google.com [172.24.189.93]) by gmr-mx.google.com with ESMTPS id x22si3301802yhd.5.2014.04.16.16.09.00 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 16 Apr 2014 16:09:00 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-2.hot.corp.google.com (Postfix) with ESMTP id DD9E35A4267; Wed, 16 Apr 2014 16:08:59 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id A2161220866; Wed, 16 Apr 2014 16:08:59 -0700 (PDT) From: Andrew Bresticker To: Stephen Warren , Thierry Reding , Chris Ball , Ulf Hansson Subject: [PATCH v2 2/3] mmc: tegra: fix reporting of base clock frequency Date: Wed, 16 Apr 2014 16:08:38 -0700 Message-Id: <1397689719-28882-3-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.9.1.423.g4596e3a In-Reply-To: <1397689719-28882-1-git-send-email-abrestic@chromium.org> References: <1397526163-20126-1-git-send-email-abrestic@chromium.org> <1397689719-28882-1-git-send-email-abrestic@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140416_160921_579079_296A7EB2 X-CRM114-Status: GOOD ( 13.40 ) X-Spam-Score: -1.4 (-) Cc: linux-tegra@vger.kernel.org, Andrew Bresticker , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra SDHCI controllers, by default, report a base clock frequency of 208Mhz in SDHCI_CAPABILTIES which may or may not be equal to the actual base clock frequency. This is because the clock rate is configured by the clock controller, which is external to the SD/MMC controller. Since the SD/MMC controller has no knowledge of how this clock is configured, it will simply report the maximum frequency. While the reported value can be overridden by setting BASE_CLK_FREQ in VENDOR_CLOCK_CTRL on Tegra30 and later SoCs, just set CAP_CLOCK_BASE_BROKEN and supply sdhci_pltfm_clk_get_max_clock(), which simply does a clk_get_rate(), as the get_max_clock() callback. Signed-off-by: Andrew Bresticker --- Changes from v1: - fixed up commit message per Stephen's suggestions --- drivers/mmc/host/sdhci-tegra.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 3cadd9c..c3f92d9 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -165,13 +165,15 @@ static const struct sdhci_ops tegra_sdhci_ops = { .write_l = tegra_sdhci_writel, .platform_bus_width = tegra_sdhci_buswidth, .platform_reset_exit = tegra_sdhci_reset_exit, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, }; static const struct sdhci_pltfm_data sdhci_tegra20_pdata = { .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .ops = &tegra_sdhci_ops, }; @@ -186,7 +188,8 @@ static const struct sdhci_pltfm_data sdhci_tegra30_pdata = { SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .ops = &tegra_sdhci_ops, }; @@ -202,7 +205,8 @@ static const struct sdhci_pltfm_data sdhci_tegra114_pdata = { SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_NO_HISPD_BIT | - SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC, + SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, .ops = &tegra_sdhci_ops, };