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Fri, 18 Apr 2014 10:15:30 +0900 (KST) From: Chanwoo Choi To: linux-kernel@vger.kernel.org Subject: [PATCHv3 6/7] dt-bindings: add documentation for Exynos3250 clock controller Date: Fri, 18 Apr 2014 10:15:27 +0900 Message-id: <1397783728-6193-7-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1397783728-6193-1-git-send-email-cw00.choi@samsung.com> References: <1397783728-6193-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupileLIzCtJLcpLzFFi42JZI2JSqLupJiDYYMUhLYu/k46xW0xad4DJ 4vJ+bYvrX56zWsw/co7Vov/NQlaLzx9a2C3OvVrJaNG74CqbxdmmN+wWmx5fY7W4vGsOm8WM 8/uYLG5f5rX4e+cfm8XS6xeZLJ5OuMhmcer6ZzaLCdPXsli8vTOdxaJ17xF2i5N/ehktnhz+ yGoxY/JLNov1M16zWBybsYTRov3vXjaLvTsnMzrIeKyZt4bRo6W5h83j969JjB6X+3qZPP6u esHssXPWXXaPlcu/sHlsXqHlsWlVJ5vHnWt7gLwl9R5XTjSxevRtWcXo8XmTXABfFJdNSmpO Zllqkb5dAldG94SfrAXzRCrmLprO3sDYIdjFyMkhIWAi0dP8gBXCFpO4cG89WxcjF4eQwFJG iVNrb7LBFD2Yew0qsYhR4s2D56wQThOTxOoHs8Gq2AS0JPa/uAFmiwgoSGzufQZWxCzQySZx /vtFsISwQLjE3Et/mUBsFgFVif1vXoDZvAIuElvn/GaEWCcn8WHPI3YQm1PAVeL84yMsILYQ UM3D79NZQIZKCHzgkFi+7jY7xCABiW+TDwElOIASshKbDjBDzJGUOLjiBssERuEFjAyrGEVT C5ILipPSiwz1ihNzi0vz0vWS83M3MQLTwel/z3p3MN4+YH2IMRlo3ERmKdHkfGA6ySuJNzQ2 M7IwNTE1NjK3NCNNWEmcN+lhUpCQQHpiSWp2ampBalF8UWlOavEhRiYOTqkGRkaFWwfljLR6 NDazKUv+mZzd9+JRyIuz+k9jZv27xxuzv3i58SYhuewtocVFHrk9uV7dv9ctenpqwqzFOUsT t1TJN0tuFij5UebNXfi//1p5ya+oL2dXxMYvtF6qwqXt2MnJXyGdpdA6s/uCgPTZHUw1bw9k Ojro7L9/osbbt07tk13TxX3lSizFGYmGWsxFxYkAX615sh0DAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOKsWRmVeSWpSXmKPExsVy+t9jAd1NNQHBBi8uKFj8nXSM3WLSugNM Fpf3a1tc//Kc1WL+kXOsFv1vFrJafP7Qwm5x7tVKRoveBVfZLM42vWG32PT4GqvF5V1z2Cxm nN/HZHH7Mq/F3zv/2CyWXr/IZPF0wkU2i1PXP7NZTJi+lsXi7Z3pLBate4+wW5z808to8eTw R1aLGZNfslmsn/GaxeLYjCWMFu1/97JZ7N05mdFBxmPNvDWMHi3NPWwev39NYvS43NfL5PF3 1Qtmj52z7rJ7rFz+hc1j8wotj02rOtk87lzbA+Qtqfe4cqKJ1aNvyypGj8+b5AL4ohoYbTJS E1NSixRS85LzUzLz0m2VvIPjneNNzQwMdQ0tLcyVFPISc1NtlVx8AnTdMnOAIaOkUJaYUwoU CkgsLlbSt8M0ITTETdcCpjFC1zckCK7HyAANJKxhzOie8JO1YJ5IxdxF09kbGDsEuxg5OSQE TCQezL3GBmGLSVy4tx7I5uIQEljEKPHmwXNWCKeJSWL1g9lgVWwCWhL7X9wAs0UEFCQ29z4D K2IW6GSTOP/9IlhCWCBcYu6lv0wgNouAqsT+Ny/AbF4BF4mtc34zQqyTk/iw5xE7iM0p4Cpx /vERFhBbCKjm4ffpLBMYeRcwMqxiFE0tSC4oTkrPNdIrTswtLs1L10vOz93ECE42z6R3MK5q sDjEKMDBqMTDe+Grf7AQa2JZcWXuIUYJDmYlEV7l0oBgId6UxMqq1KL8+KLSnNTiQ4zJQFdN ZJYSTc4HJsK8knhDYxMzI0sjc0MLI2Nz0oSVxHkPtloHCgmkJ5akZqemFqQWwWxh4uCUamBU ld1lZulcptC1vEipjkGVjZNv3ymV4AV2nQd3a7yakWSiyiz+RlhetZD5UvxKXZnnPj++NnN8 tIpOYG5qXXzz6L1lN1v/8QZtPzCzvfZ1oMgmazXZ/MKUP9e2Tlvks7XgxovylxJV/t13HghO fRT88t307Tn5Nae6bu9p1hKcNyOyQ+6JWqoSS3FGoqEWc1FxIgC6OeryegMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140417_181555_863774_C67E5911 X-CRM114-Status: GOOD ( 10.27 ) X-Spam-Score: -5.7 (-----) Cc: Mark Rutland , Randy Dunlap , t.figa@samsung.com, tushar.behera@linaro.org, sajjan.linux@gmail.com, kgene.kim@samsung.com, linux@arm.linux.org.uk, Pawel Moll , sachin.kamat@linaro.org, cw00.choi@samsung.com, thomas.abraham@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, arnd@arndb.de, Ian Campbell , marc.zyngier@arm.com, Rob Herring , ben-linux@fluff.org, Mike Turquette , linux-samsung-soc@vger.kernel.org, hyunhee.kim@samsung.com, sw0312.kim@samsung.com, yj44.cho@samsung.com, kyungmin.park@samsung.com, Kumar Gala , olof@lixom.net, chanho61.park@samsung.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Exynos3250 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Cc: Mike Turquette Cc: Kukjin Kim Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Randy Dunlap Cc: Tomasz Figa Signed-off-by: Chanwoo Choi Signed-off-by: Tomasz Figa Acked-by: Kyungmin Park --- .../devicetree/bindings/clock/exynos3250-clock.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos3250-clock.txt diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt new file mode 100644 index 0000000..aadc9c5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt @@ -0,0 +1,41 @@ +* Samsung Exynos3250 Clock Controller + +The Exynos3250 clock controller generates and supplies clock to various +controllers within the Exynos3250 SoC. + +Required Properties: + +- compatible: should be one of the following. + - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. + +All available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos3250.h header and can be used in device +tree sources. + +Example 1: An example of a clock controller node is listed below. + + cmu: clock-controller@10030000 { + compatible = "samsung,exynos3250-cmu"; + reg = <0x10030000 0x20000>; + #clock-cells = <1>; + }; + +Example 2: UART controller node that consumes the clock generated by the clock + controller. Refer to the standard clock bindings for information + about 'clocks' and 'clock-names' property. + + serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = <0 109 0>; + clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + };