From patchwork Mon Apr 21 10:41:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 4023611 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B7FD89F319 for ; Mon, 21 Apr 2014 10:44:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CC528202FE for ; Mon, 21 Apr 2014 10:44:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A1B50202EB for ; Mon, 21 Apr 2014 10:44:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WcBfw-0002Wp-VE; Mon, 21 Apr 2014 10:42:12 +0000 Received: from perceval.ideasonboard.com ([95.142.166.194]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WcBfp-0002AJ-Gt for linux-arm-kernel@lists.infradead.org; Mon, 21 Apr 2014 10:42:06 +0000 Received: from avalon.ideasonboard.com (147.20-200-80.adsl-dyn.isp.belgacom.be [80.200.20.147]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 7985E359FB; Mon, 21 Apr 2014 12:39:31 +0200 (CEST) From: Laurent Pinchart To: linux-omap@vger.kernel.org Subject: [PATCH 1/2] ARM: dts: use ti, fixed-factor-clock for dpll4_m5x2_mul_ck Date: Mon, 21 Apr 2014 12:41:46 +0200 Message-Id: <1398076907-2901-2-git-send-email-laurent.pinchart@ideasonboard.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1398076907-2901-1-git-send-email-laurent.pinchart@ideasonboard.com> References: <1398076907-2901-1-git-send-email-laurent.pinchart@ideasonboard.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140421_034205_764925_F248B97C X-CRM114-Status: GOOD ( 10.31 ) X-Spam-Score: -0.7 (/) Cc: Tomi Valkeinen , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We need to use set-rate-parent for dpll4_m5 clock path, so use the ti,fixed-factor-clock version which supports set-rate-parent property. The set-rate-parent flag itself is set in the following patch, this one just changes the clock driver to ti,fixed-factor-clock without any other changes. Signed-off-by: Laurent Pinchart --- arch/arm/boot/dts/omap36xx-clocks.dtsi | 2 +- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi index 6b5280d..200ae3a 100644 --- a/arch/arm/boot/dts/omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi @@ -83,7 +83,7 @@ }; &dpll4_m5x2_mul_ck { - clock-mult = <1>; + ti,clock-mult = <1>; }; &dpll4_m6x2_mul_ck { diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 12be2b3..351f58b 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -453,10 +453,10 @@ dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { #clock-cells = <0>; - compatible = "fixed-factor-clock"; + compatible = "ti,fixed-factor-clock"; clocks = <&dpll4_m5_ck>; - clock-mult = <2>; - clock-div = <1>; + ti,clock-mult = <2>; + ti,clock-div = <1>; }; dpll4_m5x2_ck: dpll4_m5x2_ck {