From patchwork Tue Apr 22 01:39:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Florian Fainelli X-Patchwork-Id: 4027951 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 133D0BFF02 for ; Tue, 22 Apr 2014 01:43:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2900B202B8 for ; Tue, 22 Apr 2014 01:43:57 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5877620265 for ; Tue, 22 Apr 2014 01:43:56 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WcPgz-0007hM-Qi; Tue, 22 Apr 2014 01:40:13 +0000 Received: from mail-pd0-x22b.google.com ([2607:f8b0:400e:c02::22b]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WcPgl-0006bs-Bh for linux-arm-kernel@lists.infradead.org; Tue, 22 Apr 2014 01:40:00 +0000 Received: by mail-pd0-f171.google.com with SMTP id r10so4263878pdi.16 for ; Mon, 21 Apr 2014 18:39:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iDFtmaywkBnUwjWcDwsAipaMgKejPLia4OwiLVBhze4=; b=Jy95Ol/vjD8fZ6T8rRTSBCAKlZ2VpBkY+oBPCaI2m20BrpUllnj1owzsACnkup8WRY raSlttNf0sZvDgDzyWL/yPh94QtAMm9AlR5LQYUuy1KtOlLzeXOZ8/mQ1ahgIeur08uZ t0xe9OWD0vAtICidDE5HcgNcbfh5r72IArtDP/g0GKyB046WCOCDnUJ4CaeSoqyFM1oe yEfVPcPEJCHZy8OcD+SiI6bQPPqv/YBHzLeo887zzzjHyib51bNbmfcQd7u8iQzM0TBx z+LCwjuwkIaZ933J9AGOWfRdoGk+pfhBcpI68uoBvDIjojiJWzbWfwAT+GzW1e3v4Exn +kUw== X-Received: by 10.66.251.233 with SMTP id zn9mr41580937pac.67.1398130778098; Mon, 21 Apr 2014 18:39:38 -0700 (PDT) Received: from fainelli-desktop.broadcom.com (5520-maca-inet1-outside.broadcom.com. [216.31.211.11]) by mx.google.com with ESMTPSA id n6sm80964520pbj.22.2014.04.21.18.39.36 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Apr 2014 18:39:37 -0700 (PDT) From: Florian Fainelli To: linux-arm-kernel@lists.infradead.org Subject: [PATCH RESEND 3/5] ARM: BCM63XX: add BCM63138 minimal Device Tree Date: Mon, 21 Apr 2014 18:39:16 -0700 Message-Id: <1398130758-19456-4-git-send-email-f.fainelli@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1398130758-19456-1-git-send-email-f.fainelli@gmail.com> References: <1398130758-19456-1-git-send-email-f.fainelli@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140421_183959_423958_E401D698 X-CRM114-Status: GOOD ( 12.15 ) X-Spam-Score: -0.1 (/) Cc: devicetree@vger.kernel.org, cernekee@gmail.com, arnd@arndb.de, bcm@fixthebug.org, mporter@linaro.org, jogo@openwrt.org, Florian Fainelli , aelder@linaro.org, olof@lixom.net, mbizon@freebox.fr, jpeshkin@broadcom.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a very minimalistic BCM63138 Device Tree include file which describes the BCM63138 SoC with only the basic set of required peripherals: - Cortex A9 CPU - ARM GIC - PL310 Level-2 cache controller - ARM TWD & Global timers - ARM TWD watchdog - legacy MIPS bus (UBUS) Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm63138.dtsi | 109 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 arch/arm/boot/dts/bcm63138.dtsi diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi new file mode 100644 index 000000000000..190d6e53a85a --- /dev/null +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -0,0 +1,109 @@ +/* + * Broadcom BCM63138 DSL SoCs Device Tree + * + * Copyright (C) 2014 Broadcom Corporation + * + * Licensed under the GNU/GPL. See COPYING for details + */ + +#include +#include + +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm63138"; + model = "Broadcom BCM63138 DSL SoC"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <500000000>; + }; + }; + + /* ARM bus */ + axi@80000000 { + compatible = "simple-bus"; + ranges = <0 0x80000000 0x783003>; + reg = <0x80000000 0x783003>; + #address-cells = <1>; + #size-cells = <1>; + + L2: cache-controller@1d000 { + compatible = "arm,pl310-cache"; + reg = <0x1d000 0x1000>; + cache-unified; + cache-level = <2>; + interrupts = ; + }; + + mpcore@1e000 { + compatible = "simple-bus"; + reg = <0x1e000 0x20000>; + ranges = <0 0x1e000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + + scu: scu@0 { + compatible = "arm,cortex-a9-scu"; + reg = <0x0 0x100>; + }; + + gic: interrupt-controller@100 { + compatible = "arm,cortex-a9-gic"; + reg = <0x1000 0x1000 + 0x100 0x100>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + }; + + global_timer: timer@200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x200 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + local_timer: local-timer@600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x600 0x20>; + interrupts = ; + clocks = <&arm_timer_clk>; + }; + + twd_watchdog: watchdog@620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x620 0x20>; + interupts = ; + }; + }; + }; + + /* Legacy UBUS base */ + ubus@fffe8000 { + compatible = "simple-bus"; + reg = <0xfffe8000 0x8053>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8053>; + }; +};