From patchwork Fri Apr 25 13:20:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 4062451 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 811069F271 for ; Fri, 25 Apr 2014 13:24:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7DD7020397 for ; Fri, 25 Apr 2014 13:24:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8440D2034F for ; Fri, 25 Apr 2014 13:24:41 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wdg4P-0006cR-Hb; Fri, 25 Apr 2014 13:21:37 +0000 Received: from mail-pa0-f50.google.com ([209.85.220.50]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wdg4M-0006JZ-0p for linux-arm-kernel@lists.infradead.org; Fri, 25 Apr 2014 13:21:35 +0000 Received: by mail-pa0-f50.google.com with SMTP id rd3so3156357pab.23 for ; Fri, 25 Apr 2014 06:21:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rsW4JQQVL2al3ex2iscTlrepw9llCoIoEkmXyfdUL2w=; b=FPclno/bYmc1CmluN287mVps5Md2cEs5WCOI/ebzna5+4I0KdytthKa0TWvhjhCvql vUUMKo9gp/8pb+fCtTVZfAHVz91dfpCgHaBa1vcXlJBX0YWnlL/J+uXslU/ayLfEzFIi VEMa4BFvpLNVQDXcQW7zQuPKlskZW6TttgzXimnTqmOsq/gLYCfwUJ38BKrk9yPPs24f cqojaUpOfCIy4TK2oesX43DZ5TIJUEKE7g0G2d21KvtV++sTyMBn6kr8DB5T7Fqgu2B1 OmgQFjKfoKYMRACnxxALmHHvgzPhfp1LJpG03pADt+LbcP/mbSFKIjKNPFGSuD6G/JrH Ai6A== X-Gm-Message-State: ALoCoQlJWiq+y7o/yLJplGgCNtgi/dl/vEMYSNL1LqDpBreXnHNibRbcVPJs4xhC32YkC+z8MyOF X-Received: by 10.68.161.101 with SMTP id xr5mr11218409pbb.168.1398432072700; Fri, 25 Apr 2014 06:21:12 -0700 (PDT) Received: from localhost ([218.17.215.175]) by mx.google.com with ESMTPSA id id10sm15970304pbc.35.2014.04.25.06.20.54 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 25 Apr 2014 06:21:12 -0700 (PDT) From: Hanjun Guo To: linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Subject: [PATCH v3 part1 01/11] ACPI / processor: Rework _PDC related stuff to make it more arch-independent Date: Fri, 25 Apr 2014 21:20:07 +0800 Message-Id: <1398432017-8506-2-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398432017-8506-1-git-send-email-hanjun.guo@linaro.org> References: <1398432017-8506-1-git-send-email-hanjun.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140425_062134_082795_79F46B33 X-CRM114-Status: GOOD ( 18.11 ) X-Spam-Score: -0.1 (/) Cc: Mark Rutland , Rob Herring , Fenghua Yu , Tony Luck , "H. Peter Anvin" , Graeme Gregory , Arnd Bergmann , Mark Brown , Catalin Marinas , linaro-acpi@lists.linaro.org, "Rafael J. Wysocki" , x86@kernel.org, Will Deacon , Olof Johansson , Hanjun Guo , Sudeep Holla , Grant Likely , linux-ia64@vger.kernel.org, Thomas Gleixner , Charles.Garcia-Tobin@arm.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00, RCVD_IN_SORBS_WEB, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP _PDC related stuff in processor_core.c is little bit X86/IA64 dependent, macros of ACPI_PDC_* are _PDC bit definitions for Intel processors, if we use these macros in processor_core.c, we will meet compile error when ACPI is enabled on ARM64. This patch reworks the code to make it more arch-independent, moving Intel related _PDC bits into architecture directory, no functional change. Cc: Tony Luck Cc: Fenghua Yu Cc: Thomas Gleixner Cc: "H. Peter Anvin" Cc: x86@kernel.org Cc: linux-ia64@vger.kernel.org Signed-off-by: Hanjun Guo Signed-off-by: Graeme Gregory Reviewed-by: Grant Likely --- arch/ia64/include/asm/acpi.h | 5 +---- arch/ia64/kernel/acpi.c | 15 +++++++++++++++ arch/x86/include/asm/acpi.h | 19 +------------------ arch/x86/kernel/acpi/cstate.c | 27 +++++++++++++++++++++++++++ drivers/acpi/processor_core.c | 19 +------------------ 5 files changed, 45 insertions(+), 40 deletions(-) diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h index d651102..d2b8b9d 100644 --- a/arch/ia64/include/asm/acpi.h +++ b/arch/ia64/include/asm/acpi.h @@ -152,10 +152,7 @@ extern int __initdata nid_to_pxm_map[MAX_NUMNODES]; #endif static inline bool arch_has_acpi_pdc(void) { return true; } -static inline void arch_acpi_set_pdc_bits(u32 *buf) -{ - buf[2] |= ACPI_PDC_EST_CAPABILITY_SMP; -} +extern void arch_acpi_set_pdc_bits(u32 *buf); #define acpi_unlazy_tlb(x) diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c index 0d407b3..23e9b40 100644 --- a/arch/ia64/kernel/acpi.c +++ b/arch/ia64/kernel/acpi.c @@ -996,3 +996,18 @@ EXPORT_SYMBOL(acpi_unregister_ioapic); * TBD when when IA64 starts to support suspend... */ int acpi_suspend_lowlevel(void) { return 0; } + +void arch_acpi_set_pdc_bits(u32 *buf) +{ + /* Enable coordination with firmware's _TSD info */ + buf[2] |= ACPI_PDC_SMP_T_SWCOORD | ACPI_PDC_EST_CAPABILITY_SMP; + + if (boot_option_idle_override == IDLE_NOMWAIT) { + /* + * If mwait is disabled for CPU C-states, the C2C3_FFH access + * mode will be disabled in the parameter of _PDC object. + * Of course C1_FFH access mode will also be disabled. + */ + buf[2] &= ~(ACPI_PDC_C_C2C3_FFH | ACPI_PDC_C_C1_FFH); + } +} diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h index c8c1e70..e9f71bc 100644 --- a/arch/x86/include/asm/acpi.h +++ b/arch/x86/include/asm/acpi.h @@ -147,24 +147,7 @@ static inline bool arch_has_acpi_pdc(void) c->x86_vendor == X86_VENDOR_CENTAUR); } -static inline void arch_acpi_set_pdc_bits(u32 *buf) -{ - struct cpuinfo_x86 *c = &cpu_data(0); - - buf[2] |= ACPI_PDC_C_CAPABILITY_SMP; - - if (cpu_has(c, X86_FEATURE_EST)) - buf[2] |= ACPI_PDC_EST_CAPABILITY_SWSMP; - - if (cpu_has(c, X86_FEATURE_ACPI)) - buf[2] |= ACPI_PDC_T_FFH; - - /* - * If mwait/monitor is unsupported, C2/C3_FFH will be disabled - */ - if (!cpu_has(c, X86_FEATURE_MWAIT)) - buf[2] &= ~(ACPI_PDC_C_C2C3_FFH); -} +extern void arch_acpi_set_pdc_bits(u32 *buf); #else /* !CONFIG_ACPI */ diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c index 4b28159..95127d0 100644 --- a/arch/x86/kernel/acpi/cstate.c +++ b/arch/x86/kernel/acpi/cstate.c @@ -16,6 +16,33 @@ #include #include +void arch_acpi_set_pdc_bits(u32 *buf) +{ + struct cpuinfo_x86 *c = &cpu_data(0); + + /* Enable coordination with firmware's _TSD info */ + buf[2] |= ACPI_PDC_SMP_T_SWCOORD | ACPI_PDC_C_CAPABILITY_SMP; + + if (cpu_has(c, X86_FEATURE_EST)) + buf[2] |= ACPI_PDC_EST_CAPABILITY_SWSMP; + + if (cpu_has(c, X86_FEATURE_ACPI)) + buf[2] |= ACPI_PDC_T_FFH; + + /* If mwait/monitor is unsupported, C2/C3_FFH will be disabled */ + if (!cpu_has(c, X86_FEATURE_MWAIT)) + buf[2] &= ~(ACPI_PDC_C_C2C3_FFH); + + if (boot_option_idle_override == IDLE_NOMWAIT) { + /* + * If mwait is disabled for CPU C-states, the C2C3_FFH access + * mode will be disabled in the parameter of _PDC object. + * Of course C1_FFH access mode will also be disabled. + */ + buf[2] &= ~(ACPI_PDC_C_C2C3_FFH | ACPI_PDC_C_C1_FFH); + } +} + /* * Initialize bm_flags based on the CPU cache properties * On SMP it depends on cache configuration diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 71e2065..5250327 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -254,9 +254,6 @@ static void acpi_set_pdc_bits(u32 *buf) buf[0] = ACPI_PDC_REVISION_ID; buf[1] = 1; - /* Enable coordination with firmware's _TSD info */ - buf[2] = ACPI_PDC_SMP_T_SWCOORD; - /* Twiddle arch-specific bits needed for _PDC */ arch_acpi_set_pdc_bits(buf); } @@ -281,7 +278,7 @@ static struct acpi_object_list *acpi_processor_alloc_pdc(void) return NULL; } - buf = kmalloc(12, GFP_KERNEL); + buf = kzalloc(12, GFP_KERNEL); if (!buf) { printk(KERN_ERR "Memory allocation error\n"); kfree(obj); @@ -309,20 +306,6 @@ acpi_processor_eval_pdc(acpi_handle handle, struct acpi_object_list *pdc_in) { acpi_status status = AE_OK; - if (boot_option_idle_override == IDLE_NOMWAIT) { - /* - * If mwait is disabled for CPU C-states, the C2C3_FFH access - * mode will be disabled in the parameter of _PDC object. - * Of course C1_FFH access mode will also be disabled. - */ - union acpi_object *obj; - u32 *buffer = NULL; - - obj = pdc_in->pointer; - buffer = (u32 *)(obj->buffer.pointer); - buffer[2] &= ~(ACPI_PDC_C_C2C3_FFH | ACPI_PDC_C_C1_FFH); - - } status = acpi_evaluate_object(handle, "_PDC", pdc_in, NULL); if (ACPI_FAILURE(status))