From patchwork Mon Apr 28 03:53:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Shijie X-Patchwork-Id: 4074991 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DBDF39F169 for ; Mon, 28 Apr 2014 04:56:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C5F392020E for ; Mon, 28 Apr 2014 04:56:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 976B82020A for ; Mon, 28 Apr 2014 04:56:17 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WedaA-000607-Ho; Mon, 28 Apr 2014 04:54:22 +0000 Received: from mail-by2lp0242.outbound.protection.outlook.com ([207.46.163.242] helo=na01-by2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WedYb-0004eD-TT; Mon, 28 Apr 2014 04:52:47 +0000 Received: from CH1PR03CA005.namprd03.prod.outlook.com (10.255.156.150) by BL2PR03MB420.namprd03.prod.outlook.com (10.141.92.25) with Microsoft SMTP Server (TLS) id 15.0.929.12; Mon, 28 Apr 2014 04:52:24 +0000 Received: from BY2FFO11FD048.protection.gbl (10.255.156.132) by CH1PR03CA005.outlook.office365.com (10.255.156.150) with Microsoft SMTP Server (TLS) id 15.0.929.12 via Frontend Transport; Mon, 28 Apr 2014 04:52:23 +0000 Received: from az84smr01.freescale.net (192.88.158.246) by BY2FFO11FD048.mail.protection.outlook.com (10.1.15.176) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Mon, 28 Apr 2014 04:52:23 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s3S4pr3b009014; Sun, 27 Apr 2014 21:52:20 -0700 From: Huang Shijie To: Subject: [PATCH v2 07/10] mtd: fsl-quadspi: add the DDR quad read support for Spansion NOR Date: Mon, 28 Apr 2014 11:53:44 +0800 Message-ID: <1398657227-20721-8-git-send-email-b32955@freescale.com> X-Mailer: git-send-email 1.7.2.rc3 In-Reply-To: <1398657227-20721-1-git-send-email-b32955@freescale.com> References: <1398657227-20721-1-git-send-email-b32955@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.246; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(428001)(377424004)(189002)(199002)(479174003)(33646001)(74662001)(74502001)(92566001)(31966008)(77096999)(89996001)(87936001)(85852003)(83072002)(44976005)(92726001)(6806004)(88136002)(76176999)(99396002)(80976001)(77982001)(50226001)(83322001)(19580405001)(93916002)(87286001)(19580395003)(36756003)(80022001)(46102001)(79102001)(48376002)(62966002)(50466002)(81542001)(4396001)(81342001)(76482001)(47776003)(20776003)(77156001)(42262001); DIR:OUT; SFP:1101; SCL:1; SRVR:BL2PR03MB420; H:az84smr01.freescale.net; FPR:A8F3D050.1C65B80D.2FE8617E.48ABFDC1.205A2; MLV:sfv; PTR:gate-az5.freescale.com; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 01952C6E96 Received-SPF: None (: freescale.com does not designate permitted sender hosts) X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140427_215246_071538_8098474D X-CRM114-Status: GOOD ( 17.98 ) X-Spam-Score: -0.7 (/) Cc: marex@denx.de, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-spi@vger.kernel.org, Huang Shijie , linux-mtd@lists.infradead.org, computersforpeace@gmail.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the DDR quad read support for the fsl-quadspi driver. Check the "spi-nor,ddr-quad-read-dummy" DT property, if the DT node is exit, it means we could enable the DDR quad read. (1) Test this patch with imx6sx-sdb board (Spansion s25fl128s) The clock rate is 66MHz. (2) The information of NOR flash: ----------------------------------------------- root@imx6qdlsolo:~# mtdinfo /dev/mtd0 mtd0 Name: 21e4000.qspi Type: nor Eraseblock size: 65536 bytes, 64.0 KiB Amount of eraseblocks: 256 (16777216 bytes, 16.0 MiB) Minimum input/output unit size: 1 byte Sub-page size: 1 byte Character device major/minor: 90:0 Bad blocks are allowed: false Device is writable: true ----------------------------------------------- (3) Test this patch set with UBIFS & bonnie++: ----------------------------------------------- ubiattach /dev/ubi_ctrl -m 0 ubimkvol /dev/ubi0 -N test -m mount -t ubifs ubi0:test tmp bonnie++ -d tmp -u 0 -s 10 -r 5 ----------------------------------------------- (4) Test this patch with mtd_speedtest.ko root@imx6qdlsolo:~# insmod mtd_speedtest.ko dev=0 ================================================= mtd_speedtest: MTD device: 0 mtd_speedtest: not NAND flash, assume page size is 512 bytes. mtd_speedtest: MTD device size 16777216, eraseblock size 65536, page size 512, count of eraseblocks 256, pages per eraseblock 128, OOB size 0 mtd_speedtest: testing eraseblock write speed mtd_speedtest: eraseblock write speed is 665 KiB/s mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 49799 KiB/s mtd_speedtest: testing page write speed mtd_speedtest: page write speed is 662 KiB/s mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 24236 KiB/s mtd_speedtest: testing 2 page write speed mtd_speedtest: 2 page write speed is 657 KiB/s mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 32637 KiB/s mtd_speedtest: Testing erase speed mtd_speedtest: erase speed is 518 KiB/s mtd_speedtest: Testing 2x multi-block erase speed mtd_speedtest: 2x multi-block erase speed is 506 KiB/s mtd_speedtest: Testing 4x multi-block erase speed mtd_speedtest: 4x multi-block erase speed is 503 KiB/s mtd_speedtest: Testing 8x multi-block erase speed mtd_speedtest: 8x multi-block erase speed is 501 KiB/s mtd_speedtest: Testing 16x multi-block erase speed mtd_speedtest: 16x multi-block erase speed is 498 KiB/s mtd_speedtest: Testing 32x multi-block erase speed mtd_speedtest: 32x multi-block erase speed is 496 KiB/s mtd_speedtest: Testing 64x multi-block erase speed mtd_speedtest: 64x multi-block erase speed is 495 KiB/s mtd_speedtest: finished ================================================= (5) Conclusion: The DDR quad read could be 49799 KiB/s. Signed-off-by: Huang Shijie --- drivers/mtd/spi-nor/fsl-quadspi.c | 62 +++++++++++++++++++++++++++++++++++-- 1 files changed, 59 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 4adf79e..a5dbc62 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -29,6 +29,9 @@ /* The registers */ #define QUADSPI_MCR 0x00 +#define MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_SHIFT 29 +#define MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_MASK \ + (1 << MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_SHIFT) #define QUADSPI_MCR_RESERVED_SHIFT 16 #define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT) #define QUADSPI_MCR_MDIS_SHIFT 14 @@ -292,7 +295,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) for (i = 0; i < QUADSPI_LUT_NUM; i++) writel(0, base + QUADSPI_LUT_BASE + i * 4); - /* Quad Read */ + /* Quad Read and DDR Quad Read*/ lut_base = SEQID_QUAD_READ * 4; op = nor->read_opcode; dm = nor->read_dummy; @@ -307,6 +310,24 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) } else { dev_err(nor->dev, "Unsupported opcode : 0x%.2x\n", op); } + } else if (nor->flash_read == SPI_NOR_DDR_QUAD) { + if (op == SPINOR_OP_READ_1_4_4_D || + op == SPINOR_OP_READ4_1_4_4_D) { + /* read mode : 1-4-4, such as Spansion s25fl128s. */ + writel(LUT0(CMD, PAD1, op) + | LUT1(ADDR_DDR, PAD4, addrlen), + base + QUADSPI_LUT(lut_base)); + + writel(LUT0(MODE_DDR, PAD4, 0xff) + | LUT1(DUMMY, PAD1, dm), + base + QUADSPI_LUT(lut_base + 1)); + + writel(LUT0(READ_DDR, PAD4, rxfifo) + | LUT1(JMP_ON_CS, PAD1, 0), + base + QUADSPI_LUT(lut_base + 2)); + } else { + dev_err(nor->dev, "Unsupported opcode : 0x%.2x\n", op); + } } /* Write enable */ @@ -368,6 +389,9 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { + case SPINOR_OP_READ_1_4_4_D: + case SPINOR_OP_READ4_1_4_4_D: + case SPINOR_OP_READ4_1_1_4: case SPINOR_OP_READ_1_1_4: return SEQID_QUAD_READ; case SPINOR_OP_WREN: @@ -558,6 +582,8 @@ static void fsl_qspi_set_map_addr(struct fsl_qspi *q) static void fsl_qspi_init_abh_read(struct fsl_qspi *q) { void __iomem *base = q->iobase; + struct spi_nor *nor = &q->nor[0]; + u32 reg, reg2; int seqid; /* AHB configuration for access buffer 0/1/2 .*/ @@ -572,9 +598,30 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) writel(0, base + QUADSPI_BUF2IND); /* Set the default lut sequence for AHB Read. */ - seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode); + seqid = fsl_qspi_get_seqid(q, nor->read_opcode); writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT, q->iobase + QUADSPI_BFGENCR); + + /* enable the DDR quad read */ + if (nor->flash_read == SPI_NOR_DDR_QUAD) { + reg = readl(q->iobase + QUADSPI_MCR); + + /* Firstly, disable the module */ + writel(reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); + + /* Set the Sampling Register for DDR */ + reg2 = readl(q->iobase + QUADSPI_SMPR); + reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK; + reg2 |= (2 << QUADSPI_SMPR_DDRSMP_SHIFT); + writel(reg2, q->iobase + QUADSPI_SMPR); + + /* Enable the module again (enable the DDR too) */ + reg |= QUADSPI_MCR_DDR_EN_MASK; + if (is_imx6sx_qspi(q)) + reg |= MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_MASK; + + writel(reg, q->iobase + QUADSPI_MCR); + } } /* We use this function to do some basic init for spi_nor_scan(). */ @@ -863,7 +910,9 @@ static int fsl_qspi_probe(struct platform_device *pdev) /* iterate the subnodes. */ for_each_available_child_of_node(dev->of_node, np) { const struct spi_device_id *id; + enum read_mode mode = SPI_NOR_QUAD; char modalias[40]; + u32 dummy = 0; /* skip the holes */ if (!has_second_chip) @@ -874,6 +923,7 @@ static int fsl_qspi_probe(struct platform_device *pdev) nor->mtd = mtd; nor->dev = dev; + nor->np = np; nor->priv = q; mtd->priv = nor; @@ -899,10 +949,16 @@ static int fsl_qspi_probe(struct platform_device *pdev) if (ret < 0) goto map_failed; + /* Can we enable the DDR Quad Read? */ + ret = of_property_read_u32(np, "spi-nor,ddr-quad-read-dummy", + &dummy); + if (!ret && dummy > 0) + mode = SPI_NOR_DDR_QUAD; + /* set the chip address for READID */ fsl_qspi_set_base_addr(q, nor); - ret = spi_nor_scan(nor, id, SPI_NOR_QUAD); + ret = spi_nor_scan(nor, id, mode); if (ret) goto map_failed;