From patchwork Mon May 5 16:26:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 4115971 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 60BC89F1E1 for ; Mon, 5 May 2014 16:30:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8A98420251 for ; Mon, 5 May 2014 16:30:38 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B3D942020F for ; Mon, 5 May 2014 16:30:37 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WhLk3-0004VD-4U; Mon, 05 May 2014 16:27:47 +0000 Received: from mail-pd0-x234.google.com ([2607:f8b0:400e:c02::234]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WhLk1-0004Ew-D4 for linux-arm-kernel@lists.infradead.org; Mon, 05 May 2014 16:27:45 +0000 Received: by mail-pd0-f180.google.com with SMTP id y10so1660463pdj.25 for ; Mon, 05 May 2014 09:27:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=nfdsgIFxvCrIBaMVx8W35DGW8U5gjRo6mMCxQ7PoiXg=; b=bp3Hwx79IU88u8sO6YJr3HQfgf3Xu5GEuFkxto4WaZ+VRMNq1c6Z2zISH7fmGyZfOB VCZ4lFO6DUw+S3zKb0r83QGbVsi5S3RuMus3x7ZWwV8Q5NPrBStrfsQKS8FvybnneabX JRCiltDMgj7HaqSAGPlkm7NzIP41h+j5tYrWxhcWt+FqjAK9j9krC/5BdOpf5kJDCA0x cPHc4bnlFYOP6tVk8+1imfUfs9LIMlKujRQZvVgMmH8IlXDrigReeHiuKDUQFOzNt0zz cy+ocili8PJpyzE6Oumw6P2kGmVE+tJzRNZVyyPLcKCcLuIow2/MbeolFH7ELCry8fby OEdQ== X-Received: by 10.66.66.108 with SMTP id e12mr74526928pat.35.1399307244550; Mon, 05 May 2014 09:27:24 -0700 (PDT) Received: from localhost.localdomain ([122.171.76.161]) by mx.google.com with ESMTPSA id f5sm74977298pat.11.2014.05.05.09.27.16 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 05 May 2014 09:27:23 -0700 (PDT) From: Abhilash Kesavan To: nicolas.pitre@linaro.org, Dave.Martin@arm.com, lorenzo.pieralisi@arm.com, daniel.lezcano@linaro.org, linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, t.figa@samsung.com, abrestic@chromium.org, thomas.ab@samsung.com, inderpal.s@samsung.com Subject: [PATCH v5 1/5] ARM: EXYNOS: Add generic cpu power control functions for all exynos based SoCs Date: Mon, 5 May 2014 21:56:57 +0530 Message-Id: <1399307221-8659-2-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1399307221-8659-1-git-send-email-a.kesavan@samsung.com> References: <1399307221-8659-1-git-send-email-a.kesavan@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140505_092745_460537_2A46F67C X-CRM114-Status: GOOD ( 14.20 ) X-Spam-Score: 0.0 (/) Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, kesavan.abhilash@gmail.com, linux-samsung-soc@vger.kernel.org, arnd@arndb.de, will.deacon@arm.com, robh+dt@kernel.org, grant.likely@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Leela Krishna Amudala Add generic cpu power control functions for exynos based SoCS for cpu power up/down and to know the cpu status. Signed-off-by: Leela Krishna Amudala --- arch/arm/mach-exynos/common.h | 3 +++ arch/arm/mach-exynos/pm.c | 36 ++++++++++++++++++++++++++++++++++++ arch/arm/mach-exynos/regs-pmu.h | 6 ++++++ 3 files changed, 45 insertions(+) diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 47cbab0..a7dbb5f 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -63,5 +63,8 @@ struct exynos_pmu_conf { }; extern void exynos_sys_powerdown_conf(enum sys_powerdown mode); +extern void exynos_cpu_powerdown(int cpu); +extern void exynos_cpu_powerup(int cpu); +extern int exynos_cpu_power_state(int cpu); #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 15af0ce..6651028 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -100,6 +100,42 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) return -ENOENT; } +/** + * exynos_cpu_powerdown : power down the specified cpu + * @cpu : the cpu to power down + * + * Power downs the specified cpu. The sequence must be finished by a + * call to cpu_do_idle() + * + */ +void exynos_cpu_powerdown(int cpu) +{ + __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); +} + +/** + * exynos_cpu_powerup : power up the specified cpu + * @cpu : the cpu to power up + * + * Power up the specified cpu + */ +void exynos_cpu_powerup(int cpu) +{ + __raw_writel(S5P_CORE_LOCAL_PWR_EN, + EXYNOS_ARM_CORE_CONFIGURATION(cpu)); +} + +/** + * exynos_cpu_power_state : returns the power state of the cpu + * @cpu : the cpu to retrieve the power state from + * + */ +int exynos_cpu_power_state(int cpu) +{ + return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & + S5P_CORE_LOCAL_PWR_EN); +} + /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 4f6a256..0bdfcbc 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -121,6 +121,12 @@ #define S5P_CHECK_SLEEP 0x00000BAD +#define EXYNOS_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) +#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ + (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) +#define EXYNOS_ARM_CORE_STATUS(_nr) \ + (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) + /* Only for EXYNOS4210 */ #define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) #define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)