From patchwork Tue May 6 22:18:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 4124471 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DB7689F23C for ; Tue, 6 May 2014 22:21:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0D9DA20142 for ; Tue, 6 May 2014 22:21:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 36CD4200BE for ; Tue, 6 May 2014 22:21:47 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Whnha-0001N7-85; Tue, 06 May 2014 22:19:06 +0000 Received: from mail-ie0-f182.google.com ([209.85.223.182]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WhnhW-0001Bu-C9 for linux-arm-kernel@lists.infradead.org; Tue, 06 May 2014 22:19:03 +0000 Received: by mail-ie0-f182.google.com with SMTP id tp5so154809ieb.13 for ; Tue, 06 May 2014 15:18:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nNrcWUxU0HsL95yM4Dp1lksCS7xHSBXnyxN+QxCAP8g=; b=GXnNKE795kEjIbWSdlmHPhi9Fz8EDlMIbNlWIfmvn7qQHdq2kv2dG8Yp/DooHcZXiB fAV6B8gH62AXa9Y1iqtw5eyuKS9xDHYf27s5voiQTuK0e8f8lsu3sJaVOnlDh7H/+LK0 FERISCZyH5vQ76N2agJpXhu96WC39ER/L85sFPQ7WkKur6yj98oJgyntW+Dmg6t7phtk a6DdygWzXd52FIUI8+swFxb/JGY8p3dNfn40ylKC+OCFeRdAjZvONMHq8IXdmQb/sWR4 1dADnE55vdkpEQSE1+KAGQXcD40pBGtd3Covt9Q/2IMbjiSzKU24xusy6ceWpDCC5ySo wrKw== X-Gm-Message-State: ALoCoQkYNoe06c9HOow/xkZ1DnZiU9IFsAtzmg1+bZLvQibHxS2u2zUMBp3bsKNgT/3Qw89WqIvD X-Received: by 10.50.2.8 with SMTP id 8mr25950243igq.32.1399414717673; Tue, 06 May 2014 15:18:37 -0700 (PDT) Received: from localhost.localdomain (c-71-195-31-37.hsd1.mn.comcast.net. [71.195.31.37]) by mx.google.com with ESMTPSA id ie20sm42878494igb.10.2014.05.06.15.18.36 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 May 2014 15:18:37 -0700 (PDT) From: Alex Elder To: mporter@linaro.org, bcm@fixthebug.org, linux@arm.linux.org.uk, devicetree@vger.kernel.org, arnd@arndb.de, sboyd@codeaurora.org Subject: [PATCH v3 1/5] devicetree: bindings: document Broadcom CPU enable method Date: Tue, 6 May 2014 17:18:29 -0500 Message-Id: <1399414713-19206-2-git-send-email-elder@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1399414713-19206-1-git-send-email-elder@linaro.org> References: <1399414713-19206-1-git-send-email-elder@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140506_151902_452817_67BD4DC9 X-CRM114-Status: GOOD ( 11.47 ) X-Spam-Score: -0.7 (/) Cc: bcm-kernel-feedback-list@broadcom.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Broadcom mobile SoCs use a ROM-implemented holding pen for controlled boot of secondary cores. A special register is used to communicate to the ROM that a secondary core should start executing kernel code. This enable method is currently used for members of the bcm281xx and bcm21664 SoC families. The use of an enable method also allows the SMP operation vector to be assigned as a result of device tree content for these SoCs. Signed-off-by: Alex Elder --- Documentation/devicetree/bindings/arm/cpus.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 333f4ae..c6a2411 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -185,6 +185,7 @@ nodes to be present and contain the properties described below. "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "brcm,bcm11351-cpu-method" - cpu-release-addr Usage: required for systems that have an "enable-method" @@ -209,6 +210,17 @@ nodes to be present and contain the properties described below. Value type: Definition: Specifies the ACC[2] node associated with this CPU. + - secondary-boot-reg + Usage: + Required for systems that have an "enable-method" + property value of "brcm,bcm11351-cpu-method". + Value type: + Definition: + Specifies the physical address of the register used to + request the ROM holding pen code release a secondary + CPU. The value written to the register is formed by + encoding the target CPU id into the low bits of the + physical start address it should jump to. Example 1 (dual-cluster big.LITTLE system 32-bit):