From patchwork Fri May 9 09:59:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shiyan X-Patchwork-Id: 4141171 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1BB27BFF02 for ; Fri, 9 May 2014 10:03:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 35F0D201ED for ; Fri, 9 May 2014 10:03:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6A82520035 for ; Fri, 9 May 2014 10:03:00 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wihag-0002Gf-A7; Fri, 09 May 2014 09:59:42 +0000 Received: from smtp30.i.mail.ru ([94.100.177.90]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WihaX-0002DX-CX for linux-arm-kernel@lists.infradead.org; Fri, 09 May 2014 09:59:34 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=1UKvOJ5nnxbRen28+SUC9+sKA0P9UiIqbzxDz+5tkuI=; b=rooJeFnr1/gtN2Fwr3ppiqGj7wVM5aZI5ztp3P4WUFzMOzkaktip3enOj6hv02ixWpVcpUX//5JkE/L1rDAM4cmRts2sl7p/C//WFhI7twX6904jPUaI5NpHOMRu7oJYU9QgZTdum+Bb2CVOY4W/vUXz/Ep19W1vhQL9u2xA2Go=; Received: from [5.18.98.0] (port=53431 helo=shc.zet) by smtp30.i.mail.ru with esmtpa (envelope-from ) id 1Wiha9-0002Kh-G5; Fri, 09 May 2014 13:59:09 +0400 From: Alexander Shiyan To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] ARM: i.MX1 clk: Add devicetree support Date: Fri, 9 May 2014 13:59:01 +0400 Message-Id: <1399629542-32387-2-git-send-email-shc_work@mail.ru> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1399629542-32387-1-git-send-email-shc_work@mail.ru> References: <1399629542-32387-1-git-send-email-shc_work@mail.ru> X-Mras: Ok X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140509_025934_041119_3B922036 X-CRM114-Status: GOOD ( 14.38 ) X-Spam-Score: -0.1 (/) Cc: Alexander Shiyan , Sascha Hauer , Shawn Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, FREEMAIL_FROM, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds devicetree support CCM module for i.MX1 (MC9328MX1) CPUs. Signed-off-by: Alexander Shiyan --- .../devicetree/bindings/clock/imx1-clock.txt | 46 ++++++++++++++++++++++ arch/arm/mach-imx/clk-imx1.c | 10 ++++- 2 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/imx1-clock.txt diff --git a/Documentation/devicetree/bindings/clock/imx1-clock.txt b/Documentation/devicetree/bindings/clock/imx1-clock.txt new file mode 100644 index 0000000..f66fe37 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx1-clock.txt @@ -0,0 +1,46 @@ +* Clock bindings for Freescale i.MX1 + +Required properties: +- compatible: Should be "fsl,imx1-ccm". +- reg: Address and length of the register set. +- interrupts: Should contain CCM interrupt. +- #clock-cells: Should be <1>. + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. The following is a full list of i.MX1 +clocks and IDs. + + Clock ID + --------------------------- + dummy 0 + clk32 1 + clk16m_ext 2 + clk16m 3 + clk32_premult 4 + prem 5 + mpll 6 + mpll_gate 7 + spll 8 + spll_gate 9 + mcu 10 + fclk 11 + hclk 12 + clk48m 13 + per1 14 + per2 15 + per3 16 + clko 17 + uart3_gate 18 + ssi2_gate 19 + brom_gate 20 + dma_gate 21 + csi_gate 22 + mma_gate 23 + usbd_gate 24 + +Examples: + clks: ccm@0021b000 { + compatible = "fsl,imx1-ccm"; + reg = <0x0021b000 0x1000>; + interrupts = <59>; + }; diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c index 602b30a..d13dce4 100644 --- a/arch/arm/mach-imx/clk-imx1.c +++ b/arch/arm/mach-imx/clk-imx1.c @@ -20,7 +20,9 @@ #include #include #include +#include #include +#include #include "clk.h" #include "common.h" @@ -57,7 +59,7 @@ int __init mx1_clocks_init(unsigned long fref) int i; clk[dummy] = imx_clk_fixed("dummy", 0); - clk[clk32] = imx_clk_fixed("clk32", fref); + clk[clk32] = imx_obtain_fixed_clock("clk32", fref); clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000); clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); @@ -120,3 +122,9 @@ int __init mx1_clocks_init(unsigned long fref) return 0; } + +static void __init mx1_clocks_init_dt(struct device_node *np) +{ + mx1_clocks_init(32768); +} +CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt);