@@ -940,6 +940,25 @@
nvidia,sys-clock-req-active-high;
};
+ usb@0,70090000 {
+ status = "okay";
+ s1p05v-supply = <&vdd_1v05_run>;
+ s3p3v-supply = <&vdd_3v3_lp0>;
+ s1p8v-supply = <&vddio_1v8>;
+ };
+
+ phy@0,7009f000 {
+ status = "okay";
+ nvidia,ss-pads = <0x3>;
+ nvidia,hsic-pads = <0x0>;
+ nvidia,utmi-pads = <0x7>;
+ nvidia,ss-port0-map = <0>;
+ nvidia,ss-port1-map = <2>;
+ vbus1-supply = <&vdd_usb1_vbus>;
+ vbus2-supply = <&vdd_run_cam>;
+ vbus3-supply = <&vdd_usb3_vbus>;
+ };
+
sdhci@0,700b0400 {
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
@@ -960,33 +979,6 @@
};
};
- usb@0,7d000000 {
- status = "okay";
- };
-
- usb-phy@0,7d000000 {
- status = "okay";
- vbus-supply = <&vdd_usb1_vbus>;
- };
-
- usb@0,7d004000 {
- status = "okay";
- };
-
- usb-phy@0,7d004000 {
- status = "okay";
- vbus-supply = <&vdd_run_cam>;
- };
-
- usb@0,7d008000 {
- status = "okay";
- };
-
- usb-phy@0,7d008000 {
- status = "okay";
- vbus-supply = <&vdd_usb3_vbus>;
- };
-
backlight: backlight {
compatible = "pwm-backlight";
Enable the XHCI host controller and XUSB PHY on Venice2. All three USB2.0 ports are owned by the XHCI controller and the two SuperSpeed ports are mapped to the external USB2.0 ports. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> --- arch/arm/boot/dts/tegra124-venice2.dts | 46 ++++++++++++++-------------------- 1 file changed, 19 insertions(+), 27 deletions(-)